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31. 发明申请

US20080111202A1 FORMING CONDUCTIVE STUD FOR SEMICONDUCTIVE DEVICES 有权
公开(公告)号：US20080111202A1
公开(公告)日：2008-05-15
申请号：US12013622
申请日：2008-01-14
申请人： Thomas Dyer , Sunfei Fang , Jiang Yan
发明人： Thomas Dyer , Sunfei Fang , Jiang Yan
IPC分类号： H01L29/78
CPC分类号： H01L21/823871 , H01L21/76895 , H01L21/76897 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/7843
摘要： Embodiments of the present invention provide a method of forming a conductive stud contacting a semiconductor device. The method includes forming a protective layer covering the semiconductor device; selectively etching an opening down through the protective layer reaching a contact area of the semiconductor device, the opening being away from a protected area of the semiconductor device; and filling the opening with a conductive material to form the conductive stud. One embodiment may further include forming a dielectric liner directly on top of the semiconductor device, and forming the protective layer on top of the dielectric liner. Embodiments of the present invention also provide a semiconductor device made thereof.

32. 发明申请

US20080102612A1 SILICIDED POLYSILICON SPACER FOR ENHANCED CONTACT AREA 失效
标题翻译：用于增强接触面积的多孔聚硅氧烷绝缘子
公开(公告)号：US20080102612A1
公开(公告)日：2008-05-01
申请号：US11552673
申请日：2006-10-25
申请人： Thomas W. Dyer , Sunfei Fang , Ja-Hum Ku , Yong Meng Lee
发明人： Thomas W. Dyer , Sunfei Fang , Ja-Hum Ku , Yong Meng Lee
IPC分类号： H01L21/44 , H01L21/425 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/4983 , H01L21/28123 , H01L21/28518 , H01L21/76897 , H01L21/823418 , H01L21/823481 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： An integrated circuit device having an increased source/drain contact area by a formed silicided polysilicon spacer. The polysilicon sidewall spacer is formed having a height less than seventy percent of said gate conductor height, and having a continuous surface silicide layer over the deep source and drain regions. The contact area is enhanced by the silicided polysilicon spacer.
摘要翻译：一种通过形成的硅化多晶硅间隔物具有增加的源/漏接触面积的集成电路器件。形成多晶硅侧壁间隔物，其高度小于所述栅极导体高度的百分之七十，并且在深源极和漏极区域上具有连续的表面硅化物层。接触面积由硅化多晶硅间隔物增强。

33. 发明申请

US20080090412A1 Pre-silicide spacer removal 失效
标题翻译：预硅化物间隔物去除
公开(公告)号：US20080090412A1
公开(公告)日：2008-04-17
申请号：US11548842
申请日：2006-10-12
申请人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Jun Jung Kim , Yaocheng Liu , Huilong Zhu
发明人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Jun Jung Kim , Yaocheng Liu , Huilong Zhu
IPC分类号： H01L21/44
CPC分类号： H01L29/665 , H01L21/32 , H01L29/6653 , H01L29/66545 , H01L29/6659
摘要： A method forms a gate conductor over a substrate, and simultaneously forms spacers on sides of the gate conductor and a gate cap on the top of the gate conductor. Isolation regions are formed in the substrate and the method implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers to form source and drain regions. The method deposits a mask over the gate conductor, the spacers, and the source and drain regions. The mask is recessed to a level below a top of the gate conductor but above the source and drain regions, such that the spacers are exposed and the source and drain regions are protected by the mask. With the mask in place, the method then safely removes the spacers and the gate cap, without damaging the source/drain regions or the isolation regions (which are protected by the mask). Next, the method removes the mask and then forms silicide regions on the gate conductor and the source and drain regions.
摘要翻译：一种方法在衬底上形成栅极导体，同时在栅极导体的侧面和栅极导体的顶部上形成栅极盖。在衬底中形成隔离区域，并且该方法将杂质注入未被栅极导体和间隔物保护的衬底的暴露区域中以形成源区和漏区。该方法在栅极导体，间隔物以及源极和漏极区域上沉积掩模。掩模凹陷到栅极导体的顶部下方但在源极和漏极区域之上的水平面，使得间隔物被暴露，并且源极和漏极区域被掩模保护。在掩模就位的情况下，该方法然后安全地去除间隔物和栅极盖，而不损坏源极/漏极区域或隔离区域（被掩模保护）。接下来，该方法移除掩模，然后在栅极导体和源极和漏极区域上形成硅化物区域。

34. 发明申请

US20080090370A1 Post-silicide spacer removal 失效
公开(公告)号：US20080090370A1
公开(公告)日：2008-04-17
申请号：US11548870
申请日：2006-10-12
申请人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Siddhartha Panda , Yong Meng Lee
发明人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Siddhartha Panda , Yong Meng Lee
IPC分类号： H01L21/331
CPC分类号： H01L21/32 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A method forms a gate conductor over a substrate, forms spacers (e.g., nitride spacers) on sides of the gate conductor, and implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers. Then the method forms a silicide on surfaces of the exposed regions of the substrate. The method forms a conformal protective layer (e.g., an oxide or other similar material) over the silicide, the spacers, and the gate conductor. Next, the method forms a non-conformal sacrificial layer (e.g., nitride or other material that can be selectively removed with respect to the protective layer) over the protective layer. A subsequent partial etching process partially etches the sacrificial layer such that relatively thinner regions of the sacrificial layer that are over the spacers are completely removed and the relatively thicker regions of the sacrificial layer that are over the substrate are not removed. The next step in the method removes only those portions of the protective layer that cover the spacers, without removing the portions of the protective layer that cover the silicide. As the spacers are now exposed and the silicide is protected by the protective and sacrificial layers, the method can safely remove the spacers without affecting the silicide.

35. 发明申请

US20080026551A1 FORMATION OF FULLY SILICIDED METAL GATE USING DUAL SELF-ALIGNED SILICIDE PROCESS 失效
标题翻译：使用双自对准硅胶工艺形成全硅酸金属门
公开(公告)号：US20080026551A1
公开(公告)日：2008-01-31
申请号：US11830277
申请日：2007-07-30
申请人： Cyril Cabral , Chester Dziobkowski , Sunfei Fang , Evgeni Gousev , Rajarao Jammy , Vijay Narayanan , Vamsi Paruchuri , Ghavam Shahidi , Michelle Steen , Clement Wann
发明人： Cyril Cabral , Chester Dziobkowski , Sunfei Fang , Evgeni Gousev , Rajarao Jammy , Vijay Narayanan , Vamsi Paruchuri , Ghavam Shahidi , Michelle Steen , Clement Wann
IPC分类号： H01L21/3205
CPC分类号： H01L29/66507 , H01L21/28097 , H01L21/823443 , H01L29/66545
摘要： An advanced gate structure that includes a filly silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.
摘要翻译：提供了一种先进的栅极结构，其包括硅化金属栅极和硅化源极和漏极区域，其中完全硅化金属栅极的厚度大于硅化物源极/漏极区域的厚度。还提供了形成高级栅极结构的方法，其中在形成硅化金属栅极区之前形成硅化源极和漏极区。

36. 发明申请

US20070254420A1 SOURCE/DRAIN IMPLANTATION AND CHANNEL STRAIN TRANSFER USING DIFFERENT SIZED SPACERS AND RELATED SEMICONDUCTOR DEVICE 审中-公开
标题翻译：使用不同尺寸的间距和相关半导体器件的源/漏极植入和通道应变传输
公开(公告)号：US20070254420A1
公开(公告)日：2007-11-01
申请号：US11380743
申请日：2006-04-28
申请人： Atul Ajmera , Christopher Baiocco , Xiangdong Chen , Thomas Dyer , Sunfei Fang , Wenzhi Gao
发明人： Atul Ajmera , Christopher Baiocco , Xiangdong Chen , Thomas Dyer , Sunfei Fang , Wenzhi Gao
IPC分类号： H01L21/338 , H01L21/20 , H01L29/76
CPC分类号： H01L21/823425 , H01L21/823412 , H01L21/823468 , H01L21/823807 , H01L21/823864 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7843
摘要： Methods for source/drain implantation and strain transfer to a channel of a semiconductor device and a related semiconductor device are disclosed. In one embodiment, the method includes using a first size spacer for deep source/drain implantation adjacent a gate region of a semiconductor device; and using a second, smaller size spacer for silicide formation adjacent the gate region and transferring strain from a stress liner to a channel underlying the gate region. One embodiment of a semiconductor device may include a gate region atop a substrate; a spacer including a spacer core and an outer spacer member about the spacer core; a deep source/drain region within the substrate and distanced from the spacer; and a silicide region within the substrate and overlapping and extending beyond the deep source/drain region, the silicide region aligned to the spacer.
摘要翻译：公开了用于源极/漏极注入和应变转移到半导体器件和相关半导体器件的沟道的方法。在一个实施例中，该方法包括使用与半导体器件的栅极区域相邻的深源极/漏极注入的第一尺寸间隔物; 并且使用第二较小尺寸的间隔物，用于邻近栅极区域的硅化物形成，并将应变从应力衬垫转移到栅极区域下方的沟道。半导体器件的一个实施例可以包括位于衬底顶部的栅极区域; 间隔件，其包括间隔件芯和围绕所述间隔件芯的外部间隔件; 衬底内的深源极/漏极区域，并远离间隔物; 以及衬底内的硅化物区域，并且重叠并延伸超过深源极/漏极区域，硅化物区域与间隔物对准。

37. 发明授权

US07151023B1 Metal gate MOSFET by full semiconductor metal alloy conversion 失效
标题翻译：金属栅极MOSFET采用全半导体金属合金转换
公开(公告)号：US07151023B1
公开(公告)日：2006-12-19
申请号：US11161372
申请日：2005-08-01
申请人： Hasan M. Nayfeh , Mahender Kumar , Sunfei Fang , Jakub T Kedzierski , Cyril Cabral, Jr.
发明人： Hasan M. Nayfeh , Mahender Kumar , Sunfei Fang , Jakub T Kedzierski , Cyril Cabral, Jr.
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/8234 , H01L21/4763 , H01L29/00
CPC分类号： H01L21/823835 , H01L21/823842 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A MOSFET structure and method of forming is described. The method includes forming a metal-containing layer that is thick enough to fully convert the semiconductor gate stack to a semiconductor metal alloy in a first MOSFET type region but only thick enough to partially convert the semiconductor gate stack to a semiconductor metal alloy in a second MOSFET type region. In one embodiment, the gate stack in a first MOSFET region is recessed prior to forming the metal-containing layer so that the height of the first MOSFET semiconductor stack is less than the height of the second MOSFET semiconductor stack. In another embodiment, the metal-containing layer is thinned over one MOSFET region relative to the other MOSFET region prior to the conversion process.
摘要翻译：描述了MOSFET结构和形成方法。该方法包括形成足够厚的含金属层，以将半导体栅极堆叠完全转换成第一MOSFET型区域中的半导体金属合金，但是仅仅足够厚以将第二半导体栅极堆叠部分地转换成半导体金属合金 MOSFET类型区域。在一个实施例中，在形成含金属层之前，第一MOSFET区域中的栅极堆叠是凹进的，使得第一MOSFET半导体堆叠的高度小于第二MOSFET半导体堆叠的高度。在另一个实施例中，在转换过程之前，含金属层相对于另一个MOSFET区域在一个MOSFET区域上变薄。

38. 发明授权

US06784105B1 Simultaneous native oxide removal and metal neutral deposition method 有权
标题翻译：同时自然氧化物去除和金属中性沉积法
公开(公告)号：US06784105B1
公开(公告)日：2004-08-31
申请号：US10410496
申请日：2003-04-09
申请人： Chih-Chao Yang , Yun Wang , Larry Clevenger , Andrew Simon , Stephen Greco , Kaushik Chanda , Terry Spooner , Andy Cowley , Sunfei Fang
发明人： Chih-Chao Yang , Yun Wang , Larry Clevenger , Andrew Simon , Stephen Greco , Kaushik Chanda , Terry Spooner , Andy Cowley , Sunfei Fang
IPC分类号： H01L2144
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76838 , H01L21/76862 , H01L21/76865
摘要： A method of fabricating a semiconductor device having a dielectric structure on which an interconnect structure is optionally patterned using lithographic and etching techniques, within a single deposition chamber, is provided. The dielectric structure may optionally be covered by diffusion barrier materials prior to a sputter etching process. This sputter etching process is used to remove the native oxide on an underneath metal conductor surface and includes a directional gaseous bombardment with simultaneous deposition of metal neutral. Diffusion barrier materials may also be deposited into the pattern.
摘要翻译：提供一种制造具有电介质结构的半导体器件的方法，其中使用光刻和蚀刻技术在单个淀积室内使互连结构任意地图案化。在溅射蚀刻工艺之前，电介质结构可任选地被扩散阻挡材料覆盖。该溅射蚀刻工艺用于去除下面的金属导体表面上的自然氧化物，并且包括具有同时沉积金属中性的定向气体轰击。扩散阻挡材料也可以沉积到图案中。

39. 发明申请

US20120171831A1 ASYMMETRIC FET INCLUDING SLOPED THRESHOLD VOLTAGE ADJUSTING MATERIAL LAYER AND METHOD OF FABRICATING SAME 有权
标题翻译：包括斜面电压调节材料层的不对称FET及其制造方法
公开(公告)号：US20120171831A1
公开(公告)日：2012-07-05
申请号：US13420730
申请日：2012-03-15
申请人： Dureseti Chidambarrao , Sunfei Fang , Yue Liang , Xiaojun Yu , Jun Yuan
发明人： Dureseti Chidambarrao , Sunfei Fang , Yue Liang , Xiaojun Yu , Jun Yuan
IPC分类号： H01L21/336 , H01L21/283
CPC分类号： H01L27/092 , H01L21/823857 , H01L29/42368 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/66583 , H01L29/78
摘要： A method of forming a semiconductor structure is provided. The method includes providing a structure including at least one dummy gate region located on a surface of a semiconductor substrate and a dielectric material layer located on sidewalls of the at least one dummy gate region. Next, a portion of the dummy gate region is removed exposing an underlying high k gate dielectric. A sloped threshold voltage adjusting material layer is then formed on an upper surface of the high k gate dielectric, and thereafter a gate conductor is formed atop the sloped threshold voltage adjusting material layer.
摘要翻译：提供一种形成半导体结构的方法。该方法包括提供包括位于半导体衬底的表面上的至少一个伪栅极区域和位于该至少一个虚拟栅极区域的侧壁上的介电材料层的结构。接下来，去除暴露下面的高k栅极电介质的虚拟栅极区域的一部分。然后在高k栅极电介质的上表面上形成倾斜的阈值电压调节材料层，然后在倾斜的阈值电压调节材料层的顶部形成栅极导体。

40. 发明授权

US08173531B2 Structure and method to improve threshold voltage of MOSFETS including a high K dielectric 有权
标题翻译：提高包括高K电介质的MOSFET的阈值电压的结构和方法
公开(公告)号：US08173531B2
公开(公告)日：2012-05-08
申请号：US12535183
申请日：2009-08-04
申请人： Sunfei Fang , Brian J. Greene , Effendi Leobandung , Qingqing Liang , Edward P. Maciejewski , Yanfeng Wang
发明人： Sunfei Fang , Brian J. Greene , Effendi Leobandung , Qingqing Liang , Edward P. Maciejewski , Yanfeng Wang
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823857 , H01L21/28247 , H01L21/823842 , H01L21/823864 , H01L29/517 , H01L29/6659 , H01L29/66636
摘要： A method of forming threshold voltage controlled semiconductor structures is provided in which a conformal nitride-containing liner is formed on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon oxide. The conformal nitride-containing liner is a thin layer that is formed using a low temperature (less than 500° C.) nitridation process.
摘要翻译：提供了形成阈值电压控制的半导体结构的方法，其中在至少暴露的具有大于氧化硅的介电常数的栅极介电材料的侧壁上形成共形氮化物衬里。含氮氮化物的内衬是使用低温（小于500℃）的氮化工艺形成的薄层。

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