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31. 发明授权

US08686563B2 Methods of forming fine patterns in the fabrication of semiconductor devices 有权
标题翻译：在半导体器件的制造中形成精细图案的方法
公开(公告)号：US08686563B2
公开(公告)日：2014-04-01
申请号：US12639542
申请日：2009-12-16
申请人： Sang-Yong Park , Jae-Hwang Sim , Young-Ho Lee , Kyung-Lyul Moon , Jae-Kwan Park
发明人： Sang-Yong Park , Jae-Hwang Sim , Young-Ho Lee , Kyung-Lyul Moon , Jae-Kwan Park
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/528 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L21/76838 , H01L21/823456 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region.
摘要翻译：在形成半导体器件的方法中，在衬底上提供特征层，并且在特征层上设置掩模层。掩模层的一部分在半导体器件的第一区域被去除，其中特征层的精细特征将被定位，掩模层保留在半导体器件的第二区域中，其中特征层的广泛特征将是位于。模具掩模图案设置在第一区域中的特征层和第二区域中的掩模层上。间隔层设置在第一区域和第二区域中的模具掩模图案上。执行蚀刻工艺以蚀刻间隔层，使得间隔物保留在模具掩模图案的图案特征的侧壁处，并且蚀刻第二区域中的掩模层以在第二区域中提供掩模层图案。使用掩模层图案作为第二区域中的蚀刻掩模蚀刻特征层，并且在第一区域中使用间隔物作为蚀刻掩模来提供在第一区域中具有精细特征的特征层图案，并且在第二区域中具有广泛特征。

32. 发明授权

US08483349B2 Spacer grid for dual-cooling nuclear fuel rods using intersectional support structures 有权
标题翻译：用于使用交叉支撑结构的双重冷却核燃料棒的间隔栅格
公开(公告)号：US08483349B2
公开(公告)日：2013-07-09
申请号：US12181891
申请日：2008-07-29
申请人： Jae-Yong Kim , Hyung-Kyu Kim , Kyung-Ho Yoon , Young-Ho Lee , Kang-Hee Lee
发明人： Jae-Yong Kim , Hyung-Kyu Kim , Kyung-Ho Yoon , Young-Ho Lee , Kang-Hee Lee
IPC分类号： G21C3/34
CPC分类号： G21C3/02 , G21C3/322 , G21C3/352 , G21C3/356 , Y02E30/38
摘要： A spacer grid for dual-cooling nuclear fuel rods arranged at a narrow interval. The spacer grid solves the problem in which, since the dual-cooling nuclear fuel rods are used to improve the cooling performance and stability of nuclear fuel and obtain high burnup and output, the outer diameter of each dual-cooling nuclear fuel rod is increased, and thus the gap between each dual-cooling nuclear fuel rod and the grid strap is decreased. The spacer grid includes first grid straps and second grid straps, which are crossed and arranged in transverse and longitudinal directions at regular intervals and have the shape of a flat strip, and support structures, which are fitted into the first and second grid straps around intersections of the first and second grid straps so as to support the dual-cooling nuclear fuel rods.
摘要翻译：用于双冷却核燃料棒的隔离栅格，其间隔狭窄。间隔栅格解决了由于双冷核燃料棒用于提高核燃料的冷却性能和稳定性并获得高燃耗和输出的问题，每个双重冷却核燃料棒的外径增加，因此，每个双重冷却核燃料棒和网格带之间的间隙减小。间隔网格包括第一网格带和第二网格带，它们以横向和纵向方向以规则的间隔交叉并布置，并且具有平坦的形状和支撑结构，其被安装在交叉点周围的第一和第二网格带中的第一和第二格栅带，以支撑双重冷却核燃料棒。

33. 发明申请

US20130072022A1 METHOD OF FORMING PATTERNS FOR SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件的图案的方法
公开(公告)号：US20130072022A1
公开(公告)日：2013-03-21
申请号：US13678930
申请日：2012-11-16
申请人： Young-Ho Lee , Jae-Hwang Sim , Sang-Yong Park , Kyung-Lyul Moon
发明人： Young-Ho Lee , Jae-Hwang Sim , Sang-Yong Park , Kyung-Lyul Moon
IPC分类号： H01L21/311
CPC分类号： H01L23/528 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/76229 , H01L21/76816 , H01L21/76838 , H01L27/10814 , H01L27/10855 , H01L27/11519 , H01L27/11526 , H01L2924/0002 , H01L2924/00
摘要： Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed. The first layer in the first and second regions are simultaneously etched by using the plurality of spacers and the blocking pattern as etch masks in the first region and using the low-density large-width pattern as an etch mask in the second region.
摘要翻译：提供一种形成半导体器件的图案的方法，其中精细图案和大幅图案同时并且彼此相邻地形成。在该方法中，在衬底上形成第一层以覆盖包括在衬底中的第一区域和第二区域。同时形成覆盖第一区域中的第一层的一部分的阻挡图案和覆盖第二区域中的第一层的一部分的低密度大图案。在第一层上形成多个牺牲掩模图案，并在第一区域中形成阻挡图案。形成覆盖多个牺牲掩模图案的暴露侧壁的多个间隔物。去除多个牺牲掩模图案。通过使用多个间隔物和阻挡图案作为第一区域中的蚀刻掩模并且在第二区域中使用低密度大宽度图案作为蚀刻掩模，同时蚀刻第一和第二区域中的第一层。

34. 发明授权

US08243872B2 Spacer grid for close-spaced nuclear fuel rods 有权
标题翻译：隔间核燃料棒的间隔栅格
公开(公告)号：US08243872B2
公开(公告)日：2012-08-14
申请号：US12146493
申请日：2008-06-26
申请人： Kang-Hee Lee , Hyung-Kyu Kim , Kyung-Ho Yoon , Young-Ho Lee , Jae-Yong Kim , Tae-Hyun Chun , Wang-Kee In , Dong-Seok Oh , Chang-Hwan Shin
发明人： Kang-Hee Lee , Hyung-Kyu Kim , Kyung-Ho Yoon , Young-Ho Lee , Jae-Yong Kim , Tae-Hyun Chun , Wang-Kee In , Dong-Seok Oh , Chang-Hwan Shin
IPC分类号： G21C3/34
CPC分类号： G21C3/352 , G21C3/322 , G21C3/3563 , Y02E30/38
摘要： A spacer grid can be applied to close-spaced nuclear fuel rods. The spacer grid is directed to solve the problem in which, as the outer diameter of each nuclear fuel rod increases due to the use of dual-cooled nuclear fuel rods for improving cooling performance and obtaining high combustion and high output power, the gap between the neighboring nuclear fuel rods is narrowed to thus make it impossible to use an existing spacer grid. The spacer grid is a combination of unit grid straps, each of which has supports for supporting each of the nuclear fuel rods set in a narrow array and has a sheet shape, which are combined with each other. The supports are located at positions shifted from the longitudinal central line of each unit grid strap toward sub-channels.
摘要翻译：间隔栅格可以应用于紧密间隔的核燃料棒。针对这种间隔格栅来解决这样一个问题，即由于使用双冷核燃料棒来提高冷却性能并获得高燃烧和高输出功率，因此每个核燃料棒的外径增加相邻的核燃料棒变窄，因此不可能使用现有的间隔栅格。间隔栅格是单元网格带的组合，每个网格带都具有支撑，用于支撑以窄阵列设置的每个核燃料棒，并且具有彼此组合的片状。支撑件位于从每个单元格栅带的纵向中心线向子通道移位的位置。

35. 发明申请

US20120132976A1 SEMICONDUCTOR DEVICES HAVING DUAL TRENCH, METHODS OF FABRICATING THE SAME, AND ELECTRONIC SYSTEM HAVING THE SAME 有权
标题翻译：具有双重TRENCH的半导体器件，其制造方法以及具有其的电子系统
公开(公告)号：US20120132976A1
公开(公告)日：2012-05-31
申请号：US13368556
申请日：2012-02-08
申请人： Dong-Won Kim , Jae-Hwang Sim , Keon-Soo Kim , Young-Ho Lee
发明人： Dong-Won Kim , Jae-Hwang Sim , Keon-Soo Kim , Young-Ho Lee
IPC分类号： H01L29/788 , H01L29/06
CPC分类号： H01L21/76229
摘要： A semiconductor device having a dual trench and methods of fabricating the same, a semiconductor module, an electronic circuit board, and an electronic system are provided. The semiconductor device includes a semiconductor substrate having a cell region including a cell trench and a peripheral region including a peripheral trench. The cell trench is filled with a core insulating material layer, and the peripheral trench is filled with a padding insulating material layer conformably formed on an inner surface thereof and a core insulating material layer formed on an inner surface of the padding insulating material layer. The core insulating material layer has a greater fluidity than the padding insulating material layer.
摘要翻译：提供具有双沟槽的半导体器件及其制造方法，半导体模块，电子电路板和电子系统。半导体器件包括具有包括单元沟道的单元区域和包括外围沟槽的周边区域的半导体衬底。电池沟槽填充有芯绝缘材料层，并且周边沟槽填充有在内表面上顺应地形成的填充绝缘材料层和形成在填充绝缘材料层的内表面上的芯绝缘材料层。芯绝缘材料层具有比填充绝缘材料层更大的流动性。

36. 发明授权

US08187935B2 Method of forming active region structure 有权
标题翻译：形成有源区结构的方法
公开(公告)号：US08187935B2
公开(公告)日：2012-05-29
申请号：US12795025
申请日：2010-06-07
申请人： Young-Ho Lee , Keon-Soo Kim , Jae-Hwang Sim , Jin-Hyun Shin , Kyung-Hoon Min
发明人： Young-Ho Lee , Keon-Soo Kim , Jae-Hwang Sim , Jin-Hyun Shin , Kyung-Hoon Min
IPC分类号： H01L21/8247
CPC分类号： H01L21/76229 , H01L21/823481 , H01L27/1052
摘要： A method of forming an active region structure includes preparing a semiconductor substrate having a cell array region and a peripheral circuit region, forming upper cell mask patterns having a line shape in the cell array region, forming first and second peripheral mask patterns in the peripheral circuit region, the first and second peripheral mask patterns being stacked in sequence and covering the peripheral circuit region, and upper surfaces of the upper cell mask patterns forming a step difference with an upper surface of the second peripheral mask pattern, forming spacers on sidewalls of the upper cell mask patterns to expose lower portions of the upper cell mask patterns and the second peripheral mask pattern, and removing the lower portions of the upper cell mask patterns using the spacers and the first and second peripheral mask patterns as an etch mask.
摘要翻译：形成有源区域结构的方法包括制备具有单元阵列区域和外围电路区域的半导体衬底，在单元阵列区域中形成具有线状的上层单元掩模图案，在外围电路中形成第一和第二外围掩模图案区域，第一外围掩模图案和第二外围掩模图案依次堆叠并覆盖外围电路区域，并且上部单元掩模图案的上表面与第二外围掩模图案的上表面形成阶梯差，在第二外围掩模图案的侧壁上形成间隔物上部单元掩模图案以暴露上部单元掩模图案和第二外围掩模图案的下部，并且使用间隔件和第一外围掩模图案和第二外围掩模图案作为蚀刻掩模去除上部单元掩模图案的下部。

37. 发明申请

US20110227231A1 SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110227231A1
公开(公告)日：2011-09-22
申请号：US13111100
申请日：2011-05-19
申请人： Young-Ho Lee , Jae-Hwang Sim , Jae-Kwan Park , Mo-Seok Kim , Jong-Min Lee , Dong-Sik Lee
发明人： Young-Ho Lee , Jae-Hwang Sim , Jae-Kwan Park , Mo-Seok Kim , Jong-Min Lee , Dong-Sik Lee
IPC分类号： H01L23/48
CPC分类号： H01L21/76816 , H01L21/31144
摘要： A semiconductor device may include plugs disposed in a zigzag pattern, interconnections electrically connected to the plugs and a protection pattern which is interposed between the plugs and the interconnections to selectively expose the plugs. The interconnections may include a connection portion which is in contact with plugs selectively exposed by the protection pattern. A method of manufacturing a semiconductor device includes, after forming a molding pattern and a mask pattern, selectively etching a protection layer using the mask pattern to form a protection pattern exposing a plug.
摘要翻译：半导体器件可以包括以锯齿形图案布置的插塞，电连接到插头的互连和插入在插头和互连之间的保护图案以选择性地暴露插头。互连可以包括与由保护图案选择性地暴露的插头接触的连接部分。制造半导体器件的方法包括：在形成模制图案和掩模图案之后，使用掩模图案选择性地蚀刻保护层以形成露出插头的保护图案。

38. 发明授权

US07968447B2 Semiconductor device and methods of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07968447B2
公开(公告)日：2011-06-28
申请号：US12465013
申请日：2009-05-13
申请人： Young-Ho Lee , Jae-Hwang Sim , Jae-Kwan Park , Mo-Seok Kim , Jong-Min Lee , Dong-Sik Lee
发明人： Young-Ho Lee , Jae-Hwang Sim , Jae-Kwan Park , Mo-Seok Kim , Jong-Min Lee , Dong-Sik Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/31144
摘要： A semiconductor device may include plugs disposed in a zigzag pattern, interconnections electrically connected to the plugs and a protection pattern which is interposed between the plugs and the interconnections to selectively expose the plugs. The interconnections may include a connection portion which is in contact with plugs selectively exposed by the protection pattern. A method of manufacturing a semiconductor device includes, after forming a molding pattern and a mask pattern, selectively etching a protection layer using the mask pattern to form a protection pattern exposing a plug.
摘要翻译：半导体器件可以包括以锯齿形图案布置的插塞，电连接到插头的互连和插入在插头和互连之间的保护图案以选择性地暴露插头。互连可以包括与由保护图案选择性地暴露的插头接触的连接部分。制造半导体器件的方法包括：在形成模制图案和掩模图案之后，使用掩模图案选择性地蚀刻保护层以形成露出插头的保护图案。

39. 发明申请

US20110073940A1 SEMICONDUCTOR DEVICE WITH ONE-SIDE-CONTACT AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：具有单面接触的半导体器件及其制造方法
公开(公告)号：US20110073940A1
公开(公告)日：2011-03-31
申请号：US12649999
申请日：2009-12-30
申请人： Jin-Ku LEE , Young-Ho Lee , Mi-Ri Lee
发明人： Jin-Ku LEE , Young-Ho Lee , Mi-Ri Lee
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7845 , H01L21/28518 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L29/41791 , H01L29/42356 , H01L29/66666 , H01L29/7827 , H01L29/7856
摘要： A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second conductive layer over the first conductive layer, forming a plurality of active regions by etching the second conductive layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench.
摘要翻译：一种制造半导体器件的方法包括：在半导体衬底上形成掺杂有用于形成电池结的杂质的第一导电层，在第一导电层上形成第二导电层，通过蚀刻第二导电层形成多个有源区和所述第一导电层，所述多个有源区域通过沟槽彼此分开，形成连接到所述第一导电层的侧壁的侧面接触，以及形成多个金属位线，每个金属位线连接到所述侧面接触和填充每个沟槽的一部分。

40. 发明申请

US20100096719A1 METHODS OF FORMING FINE PATTERNS IN INTEGRATED CIRCUIT DEVICES 有权
标题翻译：在集成电路设备中形成精细图案的方法
公开(公告)号：US20100096719A1
公开(公告)日：2010-04-22
申请号：US12418023
申请日：2009-04-03
申请人： Young-Ho Lee , Jae-Kwan Park , Jae-Hwang Sim , Sang-Yong Park
发明人： Young-Ho Lee , Jae-Kwan Park , Jae-Hwang Sim , Sang-Yong Park
IPC分类号： H01L29/06 , H01L21/762 , H01L23/544
CPC分类号： H01L27/0207 , H01L21/0332 , H01L21/0337 , H01L21/3081 , H01L21/3086 , H01L21/32139 , H01L21/76229 , H01L23/544 , H01L27/1052 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L2924/0002 , H01L2924/14 , H01L2924/00
摘要： A method of fabricating an integrated circuit device includes forming first and second mask structures on respective first and second regions of a feature layer. Each of the first and second mask structures includes a dual mask pattern and an etch mask pattern thereon having an etch selectivity relative to the dual mask pattern. The etch mask patterns of the first and second mask structures are isotropically etched to remove the etch mask pattern from the first mask structure while maintaining at least a portion of the etch mask pattern on the second mask structure. Spacers are formed on opposing sidewalls of the first and second mask structures. The first mask structure is selectively removed from between the spacers in the first region using the portion of the etch mask pattern on the second mask structure as a mask to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers with the second mask structure therebetween in the second region. The feature layer may be patterned using the first mask pattern as a mask to define a first feature on the first region, and using the second mask pattern as a mask to define a second feature on the second region having a greater width than the first feature.
摘要翻译：制造集成电路器件的方法包括在特征层的相应的第一和第二区域上形成第一和第二掩模结构。第一和第二掩模结构中的每一个包括双掩模图案和其上具有相对于双掩模图案的蚀刻选择性的蚀刻掩模图案。各向同性蚀刻第一和第二掩模结构的蚀刻掩模图案以从第一掩模结构去除蚀刻掩模图案，同时将蚀刻掩模图案的至少一部分保持在第二掩模结构上。间隔件形成在第一和第二掩模结构的相对侧壁上。使用第二掩模结构上的蚀刻掩模图案的部分作为掩模，第一掩模结构从第一区域中的间隔物之间选择性地移除，以限定第一掩模图案，其包括在第一区域中具有空隙的相对的侧壁间隔物以及第二掩模图案，其包括在第二区域中具有第二掩模结构的相对的侧壁间隔物。可以使用第一掩模图案作为掩模来对特征层进行图案化，以在第一区域上限定第一特征，并且使用第二掩模图案作为掩模来限定具有比第一特征宽的宽度的第二区域上的第二特征。

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