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31. 发明申请

US20150089162A1 DISTRIBUTED MEMORY OPERATIONS 审中-公开
标题翻译：分布式存储器操作
公开(公告)号：US20150089162A1
公开(公告)日：2015-03-26
申请号：US14037468
申请日：2013-09-26
申请人： Bushra Ahsan , Michael C. Adler , Neal C. Crago , Joel S. Emer , Aamer Jaleel , Angshuman Parashar , Michael I. Pellauer
发明人： Bushra Ahsan , Michael C. Adler , Neal C. Crago , Joel S. Emer , Aamer Jaleel , Angshuman Parashar , Michael I. Pellauer
IPC分类号： G06F3/06
CPC分类号： G06F13/1663 , G06F12/0646 , G06F13/1652 , G06F13/1684 , G06F2213/00
摘要： A technology for implementing a method for distributed memory operations. A method of the disclosure includes obtaining distributed channel information for an algorithm to be executed by a plurality of spatially distributed processing elements. For each distributed channel in the distributed channel information, the method further associates one or more of the plurality of spatially distributed processing elements with the distributed channel based on the algorithm.
摘要翻译：一种实现分布式存储器操作方法的技术。本公开的方法包括获得要由多个空间分布的处理元件执行的算法的分布式信道信息。对于分布式信道信息中的每个分布式信道，该方法还基于该算法进一步将多个空间分布处理单元中的一个或多个与分布式信道相关联。

32. 发明申请

US20140215162A1 RETRIEVAL OF PREVIOUSLY ACCESSED DATA IN A MULTI-CORE PROCESSOR 有权
标题翻译：在多核处理器中检索先前访问的数据
公开(公告)号：US20140215162A1
公开(公告)日：2014-07-31
申请号：US13995283
申请日：2011-12-28
申请人： Simon C. Steeley, JR. , William C. Hasenplaugh , Joel S. Emer
发明人： Simon C. Steeley, JR. , William C. Hasenplaugh , Joel S. Emer
IPC分类号： G06F12/08
CPC分类号： G06F12/0822 , G06F12/0817 , G06F12/0846 , G06F13/00 , G06F13/10 , G06F13/385
摘要： A multi-core processing apparatus may provide a cache probe and data retrieval method. The method may comprise sending a memory request from a requester to a record keeping structure. The memory request may have a memory address of a memory that stores requested data. The method may further comprise determining a last accessor of the memory address, sending a cache probe to the last accessor, determining the last accessor no longer has a copy of the line; and sending a request for the previously accessed version of the line. The request may bypass the tag-directories and obtain the requested data from memory.
摘要翻译：多核处理装置可以提供高速缓存探针和数据检索方法。该方法可以包括将请求者的存储器请求发送到记录保存结构。存储器请求可以具有存储请求的数据的存储器的存储器地址。该方法还可以包括确定存储器地址的最后存取器，向最后一个存取器发送高速缓存探测器，确定最后一个访问器不再具有该行的副本; 并发送对先前访问版本的行的请求。该请求可以绕过标签目录并从存储器获取所请求的数据。

33. 发明申请

US20120159077A1 METHOD AND APPARATUS FOR OPTIMIZING THE USAGE OF CACHE MEMORIES 有权
标题翻译：优化缓存使用的方法和设备
公开(公告)号：US20120159077A1
公开(公告)日：2012-06-21
申请号：US12974907
申请日：2010-12-21
申请人： SIMON C. STEELY, JR. , Joel S. Emer , William C. Hasenplaugh
发明人： SIMON C. STEELY, JR. , Joel S. Emer , William C. Hasenplaugh
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0804 , G06F12/0815 , G06F2212/1028 , Y02D10/13
摘要： A method and apparatus to reduce unnecessary write backs of cached data to a main memory and to optimize the usage of a cache memory tag directory. In one embodiment of the invention, the power consumption of a processor can be saved by eliminating write backs of cache memory lines that has information that has reached its end-of-life. In one embodiment of the invention, when a processing unit is required to clear one or more cache memory lines, it uses a write-zero command to clear the one or more cache memory lines. The processing unit does not perform a write operation to move or pass data values of zero to the one or more cache memory lines. By doing so, it reduces the power consumption of the processing unit.
摘要翻译：一种减少对主存储器的缓存数据的不必要的回写并优化高速缓存存储器标签目录的使用的方法和装置。在本发明的一个实施例中，通过消除具有已经达到其使用寿命的信息的高速缓冲存储器线的写回，可以节省处理器的功耗。在本发明的一个实施例中，当需要处理单元来清除一个或多个高速缓存存储器线时，它使用写入零命令来清除一个或多个高速缓存存储器线。处理单元不执行写入操作以将数据值0移动或传递给一个或多个高速缓存存储器线。通过这样做，它降低了处理单元的功耗。

34. 发明授权

US06704861B1 Mechanism for executing computer instructions in parallel 失效
标题翻译：并行执行计算机指令的机制
公开(公告)号：US06704861B1
公开(公告)日：2004-03-09
申请号：US08752729
申请日：1996-11-19
申请人： Francis X. McKeen , Michael C. Adler , Joel S. Emer , Robert P. Nix , David J. Sager , P. Geoffrey Lowney
发明人： Francis X. McKeen , Michael C. Adler , Joel S. Emer , Robert P. Nix , David J. Sager , P. Geoffrey Lowney
IPC分类号： G06F938
CPC分类号： G06F9/3842 , G06F9/3851 , G06F9/3865
摘要： A mechanism for executing computer instructions in parallel includes a compiler for generating and grouping instructions into a plurality of sets of instructions to be executed in parallel, each set having a unique identification. A computer system having a real state and a speculative state executes the sets in parallel, the computer system executing a particular set of instructions in the speculative state if the instructions of the particular set have dependencies which can not be resolved until the instructions are actually executed. The computer system generates speculative data while executing instructions in the speculative state. Logic circuits are provided to detect any exception conditions which occur while executing the particular set in the speculative state. If the particular set is subject to an exception condition, the instructions of the set are re-executed to resolve the exception condition, and to incorporate the speculative data in the real state of the computer system.
摘要翻译：用于并行执行计算机指令的机构包括：编译器，用于将指令生成和分组成并行执行的多组指令，每组具有唯一的标识。具有实际状态和推测状态的计算机系统并行地执行集合，如果特定集合的指令具有在实际执行指令之前无法解析的依赖关系，则计算机系统在推测状态下执行特定指令集。计算机系统在推测状态下执行指令时生成推测数据。提供逻辑电路以检测在推测状态下执行特定集合时发生的任何异常情况。如果特定集合受到异常条件的影响，则重新执行该集合的指令以解决异常条件，并将推测数据并入计算机系统的实际状态。

35. 发明授权

US06675192B2 Temporary halting of thread execution until monitoring of armed events to memory location identified in working registers 有权
标题翻译：临时停止线程执行，直到在工作寄存器中识别的内存位置监视武装事件
公开(公告)号：US06675192B2
公开(公告)日：2004-01-06
申请号：US10293975
申请日：2002-11-11
申请人： Joel S. Emer , Rebecca L. Stamm , Bruce E. Edwards , Matthew H. Reilly , Craig B. Zilles , Tryggve Fossum , Christopher F. Joerg , James E. Hicks, Jr.
发明人： Joel S. Emer , Rebecca L. Stamm , Bruce E. Edwards , Matthew H. Reilly , Craig B. Zilles , Tryggve Fossum , Christopher F. Joerg , James E. Hicks, Jr.
IPC分类号： G06F948
CPC分类号： G06F9/30087 , G06F9/3009 , G06F9/3851 , G06F9/485 , G06F9/526 , Y02D10/24
摘要： Execution of a program's instructions in a simultaneous multithreaded processor is halted while the program is waiting for one or more events to occur by first arming an event monitor upon an arm instruction, that is, identifying to the event monitor one or more events to be monitored, such as a modification to a value or state of an identified memory location or group of locations, and setting a watch flag to indicate enable the event monitor. Upon execution of a quiesce request instruction, the program quiesces if the watch flag is set, and a timer is started. Upon observation by the event monitor of an identified event, or upon expiration of the timer, the watch flag is cleared and execution of the program resumes.
摘要翻译：当程序正在等待一个或多个事件发生时，程序在同步多线程处理器中的指令的执行是通过在手臂指令上首先布防事件监视器来进行的，也就是识别事件监视器要监视的一个或多个事件，例如对所识别的存储器位置或一组位置的值或状态的修改，以及设置监视标志以指示启用事件监视器。在执行静默请求指令时，如果设置了监视标志，并且启动了定时器，则该程序静止。在通过事件监视器对所识别的事件进行观察时，或者在定时器到期时，清除监视标志并重新执行程序。

36. 发明授权

US5933860A Multiprobe instruction cache with instruction-based probe hint generation and training whereby the cache bank or way to be accessed next is predicted 失效
标题翻译：多指针指令缓存，具有基于指令的探针提示生成和训练，从而预测缓存库或接下来要访问的方式
公开(公告)号：US5933860A
公开(公告)日：1999-08-03
申请号：US902487
申请日：1997-07-29
申请人： Joel S. Emer , Simon Steely , Edward J. McLellan
发明人： Joel S. Emer , Simon Steely , Edward J. McLellan
IPC分类号： G06F9/38 , G06F12/08 , G06F9/34 , G06F12/06
CPC分类号： G06F9/3806 , G06F12/0862 , G06F9/3824 , G06F9/3832 , G06F2212/6082
摘要： A computer system including an instruction cache (I-cache) having a plurality of banks for storing a subset of data from memory is shown to include a prediction mechanism for predicting which bank of the I-cache contains the required data. A prediction value, including a sequential prediction hint and a branch prediction hint, is associated with each instruction stored in the I-cache. The prediction value may either be stored with the I-cache data, or in a separate memory included before the I-cache. If the predicted value is incorrect, the predicted hint is `trained` to provide a higher degree of accuracy for repetitive instruction stream operation. Processor performance is additionally improved by providing a branch hint that allows for smoother transition between changing instruction streams.
摘要翻译：包括具有用于存储来自存储器的数据子集的多个存储体的指令高速缓存（I缓存）的计算机系统被示为包括用于预测I缓存的哪个存储体包含所需数据的预测机制。包括顺序预测提示和分支预测提示的预测值与存储在I缓存中的每个指令相关联。可以将预测值与I缓存数据一起存储，或者存储在I缓存之前的单独的存储器中。如果预测值不正确，则预测提示被“训练”，以为重复的指令流操作提供更高的准确度。通过提供一个分支提示，可以更改处理器性能，从而在更改指令流之间实现更平滑的转换。

37. 发明授权

US10102124B2 High bandwidth full-block write commands 有权
公开(公告)号：US10102124B2
公开(公告)日：2018-10-16
申请号：US13993716
申请日：2011-12-28
申请人： Simon C. Steely, Jr. , William C. Hasenplaugh , Joel S. Emer , Samantika Subramaniam
发明人： Simon C. Steely, Jr. , William C. Hasenplaugh , Joel S. Emer , Samantika Subramaniam
IPC分类号： G06F13/00 , G06F12/0808 , G06F13/28
摘要： A micro-architecture may provide a hardware and software of a high bandwidth write command. The micro-architecture may invoke a method to perform the high bandwidth write command. The method may comprise sending a write request from a requester to a record keeping structure. The write request may have a memory address of a memory that stores requested data. The method may further determine copies of the requested data being present in a distributed cache system outside the memory, sending invalidation requests to elements holding copies of the requested data in the distributed cache system, sending a notification to the requester to inform presence of copies of the requested data and sending a write response message after a latest value of the requested data and all invalidation acknowledgements have been received.

38. 发明授权

US09418016B2 Method and apparatus for optimizing the usage of cache memories 有权
标题翻译：用于优化高速缓存存储器的使用的方法和装置
公开(公告)号：US09418016B2
公开(公告)日：2016-08-16
申请号：US12974907
申请日：2010-12-21
申请人： Simon C. Steely, Jr. , Joel S. Emer , William C. Hasenplaugh
发明人： Simon C. Steely, Jr. , Joel S. Emer , William C. Hasenplaugh
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F12/0891 , G06F12/0804 , G06F12/0815 , G06F2212/1028 , Y02D10/13
摘要： A method and apparatus to reduce unnecessary write backs of cached data to a main memory and to optimize the usage of a cache memory tag directory. In one embodiment of the invention, the power consumption of a processor can be saved by eliminating write backs of cache memory lines that has information that has reached its end-of-life. In one embodiment of the invention, when a processing unit is required to clear one or more cache memory lines, it uses a write-zero command to clear the one or more cache memory lines. The processing unit does not perform a write operation to move or pass data values of zero to the one or more cache memory lines. By doing so, it reduces the power consumption of the processing unit.
摘要翻译：一种减少对主存储器的缓存数据的不必要的回写并优化高速缓存存储器标签目录的使用的方法和装置。在本发明的一个实施例中，通过消除具有已经达到其使用寿命的信息的高速缓冲存储器线的写回，可以节省处理器的功耗。在本发明的一个实施例中，当需要处理单元来清除一个或多个高速缓存存储器线时，它使用写入零命令来清除一个或多个高速缓存存储器线。处理单元不执行写入操作以将数据值0移动或传递给一个或多个高速缓存存储器线。通过这样做，它降低了处理单元的功耗。

39. 发明申请

US20140052920A1 DOMAIN STATE 有权
标题翻译：域名
公开(公告)号：US20140052920A1
公开(公告)日：2014-02-20
申请号：US13995991
申请日：2011-12-29
申请人： Simon C. Steely, JR. , William C. Hasenplaugh , Joel S. Emer
发明人： Simon C. Steely, JR. , William C. Hasenplaugh , Joel S. Emer
IPC分类号： G06F12/08
CPC分类号： G06F12/0802 , G06F12/0811 , G06F12/0817 , G06F13/00
摘要： Method and apparatus to efficiently maintain cache coherency by reading/writing a domain state field associated with a tag entry within a cache tag directory. A value may be assigned to a domain state field of a tag entry in a cache tag directory. The cache tag directory may belong to a hierarchy of cache tag directories.Each tag entry may be associated with a cache line from a cache belonging to a first domain. The first domain may contain multiple caches. The value of the domain state field may indicate whether its associated cache line can be read or changed.
摘要翻译：通过读/写与缓存标签目录中的标签条目相关联的域状态字段来有效地维持高速缓存一致性的方法和装置。可以将值分配给缓存标签目录中的标签条目的域状态字段。缓存标签目录可能属于高速缓存标签目录的层次结构。每个标签条目可以与来自属于第一域的高速缓存行相关联。第一个域可能包含多个缓存。域状态字段的值可以指示其相关联的高速缓存行是否可以被读取或改变。

40. 发明授权

US07404070B1 Branch prediction combining static and dynamic prediction techniques 失效
标题翻译：分支预测结合静态和动态预测技术
公开(公告)号：US07404070B1
公开(公告)日：2008-07-22
申请号：US09723687
申请日：2000-11-28
申请人： Harish G. Patil , Joel S. Emer , Stephen Felix
发明人： Harish G. Patil , Joel S. Emer , Stephen Felix
IPC分类号： G06F9/00
CPC分类号： G06F9/382 , G06F9/3005 , G06F9/3846 , G06F9/3848
摘要： A computer system comprises a processor that comprises a hardware branch predictor and software instructions executed by the processor. The software instructions comprise conditional branch instructions and separate static branch prediction instructions. The static branch prediction instructions comprise a plurality of groups of static branch prediction bits, each group being configurable to provide prediction information for a separate conditional branch instruction.
摘要翻译：计算机系统包括处理器，其包括由处理器执行的硬件分支预测器和软件指令。软件指令包括条件分支指令和单独的静态分支预测指令。静态分支预测指令包括多组静态分支预测比特，每组可配置为单独的条件分支指令提供预测信息。

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