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    • 31. 发明申请
    • Two-Level RAM Lookup Table for Block and Page Allocation and Wear-Leveling in Limited-Write Flash-Memories
    • 有限写入闪存中的块和页面分配和磨损均衡的两级RAM查找表
    • US20070204128A1
    • 2007-08-30
    • US11742270
    • 2007-04-30
    • Charles LeeFrank YuDavid Chow
    • Charles LeeFrank YuDavid Chow
    • G06F12/00
    • G06F12/0246G06F2212/1036G06F2212/7211
    • A restrictive multi-level-cell (MLC) flash memory prohibits regressive page-writes. When a regressive page-write is requested, an empty block having a low wear-level count is found, and data from the regressive page-write and data from pages stored in the old block are written to the empty block in page order. The old block is erased and recycled. A two-level look-up table is stored in volatile random-access memory (RAM). A logical page address from a host is divided by a modulo divider to generate a quotient and a remainder. The quotient is a logical block address that indexes a first-level look-up table to find a mapping entry with a physical block address that selects a row in a second-level look-up table. The remainder locates a column in the row in the second-level look-up table. If any page-valid bits above the column pointed to by the remainder are set, the write is regressive.
    • 限制性多电平单元(MLC)闪存禁止回归页面写入。 当请求回归页面写入时,找到具有低磨损级别计数的空块,并且按页顺序将存储在旧块中的页面写入的数据和来自页面的页面的数据写入空块。 旧区被擦除并回收。 两级查找表存储在易失性随机存取存储器(RAM)中。 来自主机的逻辑页地址由模分隔器除以生成商和余数。 商是一个逻辑块地址,其索引第一级查找表以找到具有在二级查找表中选择行的物理块地址的映射条目。 剩余部分在二级查找表中的行中找到一列。 如果设置了剩余部分指向的列之上的任何页面有效位,则写入是回归的。
    • 32. 发明申请
    • MEMORY DEVICE, CIRCUITS AND METHODS FOR READING A MEMORY DEVICE
    • 用于读取存储器件的存储器件,电路和方法
    • US20070091664A1
    • 2007-04-26
    • US11561972
    • 2006-11-21
    • David ChowHans DahlTrygve Willassen
    • David ChowHans DahlTrygve Willassen
    • G11C11/22
    • G11C11/22
    • A ferroelectric memory comprises a plurality of memory cells and circuitry to sense data thereof. Power supply decoupling circuitry may decouple supplies of the memory device during a portion of reading data. Additionally, ferroelectric domains of the memory cells may receive a series of polarization reversals to improve domain alignment and malleability. To drive reference cells of the memory with such polarization reversals, a multiplexer may be configured to swap a data bitline with a reference bitline so that reference cells may be accessed as regular data cells. While reading a ferroelectric memory, a self-timer circuit may monitor characteristics of the ferroelectric material and adjust an integration duration for a sense amplifier based on the monitored characteristics. A sampling-comparator may sample a signal related to the ferroelectric material at one instant, which may then be used subsequently thereafter by the self-timer circuit to influence an integration duration of the sense amplifier.
    • 铁电存储器包括多个存储器单元和用于感测其数据的电路。 在读取数据的一部分期间,电源去耦电路可以解耦存储器件的电源。 此外,存储器单元的铁电畴可以接收一系列极化反转以改善畴对准和延展性。 为了以这样的极化反转来驱动存储器的参考单元,可以将多路复用器配置成与参考位线交换数据位线,使得参考单元可以作为常规数据单元被访问。 在读取铁电存储器的同时,自拍定时器电路可以监测铁电材料的特性,并且基于所监视的特性来调整感测放大器的积分持续时间。 采样比较器可以在一瞬间对与铁电材料相关的信号进行采样,随后可以由自拍定时器电路使用该信号来影响读出放大器的积分持续时间。