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31. 发明授权

US06486702B1 Embedded memory blocks for programmable logic 有权
标题翻译：用于可编程逻辑的嵌入式存储块
公开(公告)号：US06486702B1
公开(公告)日：2002-11-26
申请号：US09609102
申请日：2000-06-30
申请人： Tony Ngai , Sergey Shumarayev , Wei-Jen Huang , Rakesh Patel , Tin Lai
发明人： Tony Ngai , Sergey Shumarayev , Wei-Jen Huang , Rakesh Patel , Tin Lai
IPC分类号： H03K19177
CPC分类号： G11C5/025 , H03K19/17736 , H03K19/1776
摘要： A high-performance programmable logic architecture has embedded memory (608). arranged at the peripheries or edges of the integrated circuit. This enhances the performance of the programmable logic integrated circuit by shortening the lengths of the programmable interconnect (748). In a specific embodiment, the memory blocks (703) are organized in rows along the top and bottom edges of the integrated circuit. The logic elements (805) can be directly programmable routed and connected to driver blocks (809) of the logic block in adjacent rows and columns. This permits fast interconnection of signals without using the global programmable interconnect resources (815, 825). Using similar direct programmable interconnections (828, 830, 835), the logic blocks can directly programmable connect to the memory blocks without using the global programmable interconnect resources. The present invention also provides technique of flexibly combining or stitching multiple memories together to form memories of a desired size.
摘要翻译：高性能可编程逻辑架构具有嵌入式存储器（608）。布置在集成电路的周边或边缘。这通过缩短可编程互连（748）的长度来增强可编程逻辑集成电路的性能。在一个具体实施例中，存储块（703）沿着集成电路的顶部和底部边缘被排列成行。逻辑元件（805）可以直接编程路由并连接到相邻行和列中的逻辑块的驱动器块（809）。这允许信号的快速互连，而不使用全局可编程互连资源（815,825）。使用类似的直接可编程互连（828,88,835），逻辑块可以直接可编程地连接到存储器块而不使用全局可编程互连资源。本发明还提供了将多个存储器灵活组合或拼接在一起以形成所需尺寸的存储器的技术。

32. 发明授权

US06342792B1 Logic module circuitry for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的逻辑模块电路
公开(公告)号：US06342792B1
公开(公告)日：2002-01-29
申请号：US09518009
申请日：2000-03-02
申请人： Wei-Jen Huang , Sergey Shumarayev , Tony Ngai , Bruce Pedersen
发明人： Wei-Jen Huang , Sergey Shumarayev , Tony Ngai , Bruce Pedersen
IPC分类号： G06F738
CPC分类号： G06F7/506 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17744 , H03K19/17792
摘要： A programmable logic integrated circuit device has logic modules with some inputs that are optimized for speed (to enhance the speed-performance of the logic modules). For example, some of the inputs may be programmably swappable within a logic module so that a speed-critical input signal can be more easily routed to a faster part of the logic module circuitry. Alternatively or in addition, drivers may be added to the logic module circuitry to improve the speed performance of some of the inputs to the logic module. The logic module may be provided with enhanced “lonely register” circuitry which allows the lonely register output signal to be fed back for use as an input to the combinatorial logic of the logic module. The registers in multiple logic modules may be directly chained to one another in a series.
摘要翻译：可编程逻辑集成电路器件具有逻辑模块，其具有针对速度优化的一些输入（以增强逻辑模块的速度性能）。例如，一些输入可以在逻辑模块内可编程地交换，使得速度至关重要的输入信号可以更容易地路由到逻辑模块电路的较快部分。或者或另外，可以将驱动器添加到逻辑模块电路中以提高逻辑模块的一些输入的速度性能。逻辑模块可以设置有增强的“孤独寄存器”电路，其允许将孤独寄存器输出信号反馈以用作逻辑模块的组合逻辑的输入。多个逻辑模块中的寄存器可以直接链接到一个系列中。

33. 发明授权

US09904476B2 Performing multiple write operations to a memory using a pending write queue/cache 有权
公开(公告)号：US09904476B2
公开(公告)日：2018-02-27
申请号：US12870596
申请日：2010-08-27
申请人： Wei-Jen Huang , Chih-Tsung Huang , Sachin Agarwal , Sha Ma
发明人： Wei-Jen Huang , Chih-Tsung Huang , Sachin Agarwal , Sha Ma
IPC分类号： G06F13/16 , G06F12/06 , G06F3/06 , G06F12/0864 , G06F11/10 , H04L12/773 , H04L12/741
CPC分类号： G06F3/0613 , G06F3/064 , G06F3/0656 , G06F3/0659 , G06F3/0674 , G06F3/0679 , G06F11/108 , G06F12/06 , G06F12/0864 , G06F13/1642 , G06F13/1673 , H04L45/60 , H04L45/745
摘要： Techniques are described for a memory device. In various embodiments, a scheduler/controller is configured to manage data as it read to or written from a memory. A memory is partitioned into a group of sub-blocks, a parity block is associated with the sub-blocks, and the sub-blocks are accessed to read data as needed. A pending write buffer is added to a group of memory sub-blocks. Such a buffer may be sized to be equal to the group of memory sub-blocks. The pending write buffer handles collisions for write accesses to the same block.

34. 发明授权

US07492188B2 Interconnection and input/output resources for programmable logic integrated circuit devices 有权
公开(公告)号：US07492188B2
公开(公告)日：2009-02-17
申请号：US11888317
申请日：2007-07-30
申请人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter J. Kazarian , Andrew Leaver , David W. Mendel , Jim Park
发明人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter J. Kazarian , Andrew Leaver , David W. Mendel , Jim Park
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： G06F7/506 , H03K19/1737 , H03K19/177 , H03K19/17728 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17792
摘要： A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

35. 发明授权

US07317332B2 Interconnection and input/output resources for programmable logic integrated circuit devices 有权
公开(公告)号：US07317332B2
公开(公告)日：2008-01-08
申请号：US11269867
申请日：2005-11-07
申请人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Victor Maruri , Rakesh Patel
发明人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Victor Maruri , Rakesh Patel
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： G06F7/506 , H03K19/1737 , H03K19/177 , H03K19/17728 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17792
摘要： A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

36. 发明申请

US20070080710A1 Interconnection resources for programmable logic integrated circuit devices 有权
公开(公告)号：US20070080710A1
公开(公告)日：2007-04-12
申请号：US11514692
申请日：2006-09-01
申请人： James Schleicher , Jim Park , Sergey Shumarayev , Bruce Pedersen , Tony Ngai , Wei-Jen Huang , Victor Maruri , Rakesh Patel
发明人： James Schleicher , Jim Park , Sergey Shumarayev , Bruce Pedersen , Tony Ngai , Wei-Jen Huang , Victor Maruri , Rakesh Patel
IPC分类号： H03K19/177
CPC分类号： G06F7/506 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17744 , H03K19/17792
摘要： A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

37. 发明授权

US07123052B2 Interconnection resources for programmable logic integrated circuit devices 有权
公开(公告)号：US07123052B2
公开(公告)日：2006-10-17
申请号：US11087377
申请日：2005-03-22
申请人： James Schleicher , Jim Park , Sergey Shumarayev , Bruce Pederson , Tony Ngai , Wei-Jen Huang , Victor Maruri , Rakesh Patel
发明人： James Schleicher , Jim Park , Sergey Shumarayev , Bruce Pederson , Tony Ngai , Wei-Jen Huang , Victor Maruri , Rakesh Patel
IPC分类号： H03K19/177
CPC分类号： G06F7/506 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17744 , H03K19/17792
摘要： A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

38. 发明授权

US06727727B2 Interconnection resources for programmable logic integrated circuit devices 失效
标题翻译：可编程逻辑集成电路器件的互连资源
公开(公告)号：US06727727B2
公开(公告)日：2004-04-27
申请号：US10299572
申请日：2002-11-18
申请人： James Schleicher , James Park , Sergey Shumarayev , Bruce Pedersen , Tony Ngai , Wei-Jen Huang , Victor Maruri , Rakesh Patel
发明人： James Schleicher , James Park , Sergey Shumarayev , Bruce Pedersen , Tony Ngai , Wei-Jen Huang , Victor Maruri , Rakesh Patel
IPC分类号： H03K190177
CPC分类号： G06F7/506 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17744 , H03K19/17792
摘要： A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.
摘要翻译：可编程逻辑器件具有许多可编程逻辑区域，以及可用于在几乎任何逻辑区域之间进行互连的相对通用的，可编程的互连资源。此外，各种类型的更多本地互连资源与每个逻辑区域相关联，以便于在相邻或附近的逻辑区域之间建立互连，而不需要使用这些互连的通用互连资源。本地互连资源通过相对直接的和因此的高速互连来支持逻辑区域的灵活聚集，优选地在逻辑区域的典型二维阵列中的水平和垂直方向。由本地互连资源提供的逻辑区域聚类选项优选地在逻辑区域阵列内是无边界的或基本无边界的。

39. 发明授权

US06480027B1 Driver circuitry for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的驱动电路
公开(公告)号：US06480027B1
公开(公告)日：2002-11-12
申请号：US09516866
申请日：2000-03-02
申请人： Tony Ngai , Sergey Shumarayev , Wei-Jen Huang
发明人： Tony Ngai , Sergey Shumarayev , Wei-Jen Huang
IPC分类号： H03K19177
CPC分类号： G06F7/506 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/1778
摘要： Driver circuitry for programmable logic devices may include a module comprising a driver and associated hardware-programmable input and/or output routing connection. Instances of the generalized driver module may be included anywhere on the programmable logic device that driver circuitry having characteristics within the capabilities of the generalized module is needed. The circuitry of each instance of the module is hardware-customized to match the driver characteristics required for that instance. Driver circuits may be distributed throughout the interconnection conductor resources of the programmable logic device in such a way as to optimize re-buffering of signals propagating through those resources.
摘要翻译：用于可编程逻辑器件的驱动器电路可以包括包括驱动器和相关联的硬件可编程输入和/或输出路由连接的模块。广义驱动器模块的实例可以包括在可编程逻辑器件的任何地方，其中需要具有广义模块能力的特性的驱动器电路。模块的每个实例的电路都是硬件自定义的，以匹配该实例所需的驱动程序特性。驱动器电路可以分布在可编程逻辑器件的整个互连导体资源中，以便优化通过这些资源传播的信号的重新缓冲。

40. 发明授权

US06469548B1 Output buffer crossing point compensation 有权
标题翻译：输出缓冲器交叉点补偿
公开(公告)号：US06469548B1
公开(公告)日：2002-10-22
申请号：US09881354
申请日：2001-06-14
申请人： Wei-Jen Huang , Kuang-Yu Chen
发明人： Wei-Jen Huang , Kuang-Yu Chen
IPC分类号： H03B100
CPC分类号： H03F1/308
摘要： A circuit comprising a current source, a first amplifier, and a second amplifier. The circuit may be used to provide for crossing point compensation of a CMOS driver as a function of a supply voltage. The current source may be configured to present a reference current. The first amplifier may be configured to (i) receive the reference current as a load, (ii) receive a first voltage, and (iii) present a second voltage responsive to the first voltage. The second amplifier may be configured to (i) receive the second voltage and (ii) change a current at a node responsive to the second voltage.
摘要翻译：一种包括电流源，第一放大器和第二放大器的电路。该电路可用于提供作为电源电压的函数的CMOS驱动器的交叉点补偿。电流源可以被配置为呈现参考电流。第一放大器可以被配置为（i）作为负载接收参考电流，（ii）接收第一电压，以及（iii）响应于第一电压呈现第二电压。第二放大器可以被配置为（i）接收第二电压，并且（ii）响应于第二电压改变节点处的电流。

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