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31. 发明申请

US20080019205A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080019205A1
公开(公告)日：2008-01-24
申请号：US11833190
申请日：2007-08-02
申请人： Masanao Yamaoka , Koichiro Ishibashi , Shigezumi Matsui , Kenichi Osada
发明人： Masanao Yamaoka , Koichiro Ishibashi , Shigezumi Matsui , Kenichi Osada
IPC分类号： G11C5/14
CPC分类号： G11C11/419 , G11C5/146 , G11C5/147 , G11C11/4125 , G11C11/417 , G11C2207/2227
摘要： A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
摘要翻译：系统LSI中的逻辑电路设置有电源开关，以便在待机时切断开关，从而减少漏电流。同时，系统LSI的SRAM电路控制衬底偏置以减少漏电流。

32. 发明授权

US07272068B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07272068B2
公开(公告)日：2007-09-18
申请号：US11500339
申请日：2006-08-08
申请人： Masanao Yamaoka , Koichiro Ishibashi , Shigezumi Matsui , Kenichi Osada
发明人： Masanao Yamaoka , Koichiro Ishibashi , Shigezumi Matsui , Kenichi Osada
IPC分类号： G11C5/14
CPC分类号： G11C11/419 , G11C5/146 , G11C5/147 , G11C11/4125 , G11C11/417 , G11C2207/2227
摘要： A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
摘要翻译：系统LSI中的逻辑电路设置有电源开关，以便在待机时切断开关，从而减少漏电流。同时，系统LSI的SRAM电路控制衬底偏置以减少漏电流。

33. 发明授权

US07123049B2 Output buffer circuit with control circuit for modifying supply voltage and transistor size 失效
标题翻译：输出缓冲电路，具有用于修改电源电压和晶体管尺寸的控制电路
公开(公告)号：US07123049B2
公开(公告)日：2006-10-17
申请号：US11188980
申请日：2005-07-26
申请人： Takashi Satou , Shigezumi Matsui , Peter Lee , Gouichi Yokomizo
发明人： Takashi Satou , Shigezumi Matsui , Peter Lee , Gouichi Yokomizo
IPC分类号： H03K19/003
CPC分类号： G06F1/3228 , G06F1/324 , G06F1/3296 , H03K19/0005 , H03K19/0016 , H04L25/0278 , H04L25/028 , H04L25/0292 , H04L25/03885 , Y02D10/126 , Y02D10/172
摘要： In this invention, a control circuit (111) controls both the power supply voltage (VDDQ) and the transistor size of the external output buffer to thereby select the lowest supply voltage that achieves the impedance matching with the transmission line (100), to thereby save bus termination by a resistor, thus consequently achieving both the lowering of the power consumption and the speeding-up in the data transmission. The power consumption during the data transmission is proportional to the square of the supply voltage. If the operational supply voltage of the external output buffer is lowered, the power consumption will be reduced accordingly. If the operational supply voltage of the external output buffer is lowered, the impedance thereof will be increased apparently; and at the same time, if the transistor size of the external output buffer is increased, the increased impedance will be decreased. By bringing the output impedance (ON-resistance) of the external output buffer into conformity with the impedance of the transmission line, it becomes possible to output the signal without distortions on the waveform.
摘要翻译：在本发明中，控制电路（111）控制电源电压（VDDQ）和外部输出缓冲器的晶体管尺寸，从而选择实现与传输线（100）的阻抗匹配的最低电源电压，从而通过电阻节省总线终端，从而实现了功耗的降低和数据传输的加速。数据传输期间的功耗与电源电压的平方成比例。如果外部输出缓冲器的工作电源电压降低，则功耗将相应降低。如果外部输出缓冲器的工作电源电压降低，其阻抗将明显增加; 并且同时，如果外部输出缓冲器的晶体管尺寸增加，则增加的阻抗将减小。通过使外部输出缓冲器的输出阻抗（导通电阻）与传输线的阻抗一致，可以在波形上输出信号而没有失真。

34. 发明授权

US07099183B2 Semiconductor device 有权
公开(公告)号：US07099183B2
公开(公告)日：2006-08-29
申请号：US11152110
申请日：2005-06-15
申请人： Masanao Yamaoka , Koichiro Ishibashi , Shigezumi Matsui , Kenichi Osada
发明人： Masanao Yamaoka , Koichiro Ishibashi , Shigezumi Matsui , Kenichi Osada
IPC分类号： G11C11/00
CPC分类号： G11C11/419 , G11C5/146 , G11C5/147 , G11C11/4125 , G11C11/417 , G11C2207/2227
摘要： A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

35. 发明申请

US20050232054A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050232054A1
公开(公告)日：2005-10-20
申请号：US11152110
申请日：2005-06-15
申请人： Masanao Yamaoka , Koichiro Ishibashi , Shigezumi Matsui , Kenichi Osada
发明人： Masanao Yamaoka , Koichiro Ishibashi , Shigezumi Matsui , Kenichi Osada
IPC分类号： G11C11/41 , G11C5/14 , G11C11/34 , G11C11/413 , G11C11/417 , G11C11/418 , H01L29/94
CPC分类号： G11C11/419 , G11C5/146 , G11C5/147 , G11C11/4125 , G11C11/417 , G11C2207/2227
摘要： A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
摘要翻译：系统LSI中的逻辑电路设置有电源开关，以便在待机时切断开关，从而减少漏电流。同时，系统LSI的SRAM电路控制衬底偏置以减少漏电流。

36. 发明申请

US20050047192A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20050047192A1
公开(公告)日：2005-03-03
申请号：US10895394
申请日：2004-07-21
申请人： Shigezumi Matsui , Takashi Sato , Kazuyuki Sakata , Tsuyoshi Yaguchi , Kenzo Kuwabara , Atsushi Nakamura , Motoo Suwa , Ryoichi Sano , Hisashi Shiota
发明人： Shigezumi Matsui , Takashi Sato , Kazuyuki Sakata , Tsuyoshi Yaguchi , Kenzo Kuwabara , Atsushi Nakamura , Motoo Suwa , Ryoichi Sano , Hisashi Shiota
IPC分类号： G06F12/00 , G06F13/16 , G06F13/42 , G06F15/78 , G11C11/22 , G11C11/401 , G11C11/407
CPC分类号： G06F13/4243 , G06F13/1689
摘要： A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface circuit determines a delay of arrival of the data strobe signal relative to the corresponding internal clock signal by using a data strobe signal inputted in a read cycle with respect to the DDR-SDRAM, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay.
摘要翻译：存储器接口电路可连接到DDR-SDRAM，其与数据选通信号一起与数据选通信号一起输出读取数据。时钟发生器产生提供给DDR-SDRAM的内部时钟信号和存储器时钟信号。存储器接口电路通过使用相对于DDR-SDRAM在读周期中输入的数据选通信号，相对于相应的内部时钟信号确定数据选通信号的到达延迟，基于信号对所读取的数据进行采样通过移位到达数据选通信号的相位来获得，并且基于到达延迟的确定结果将采样的读取数据与相应的内部时钟信号同步。

37. 发明授权

US06434691B1 Cell phones with instruction pre-fetch buffers allocated to low bit address ranges and having validating flags 有权
公开(公告)号：US06434691B1
公开(公告)日：2002-08-13
申请号：US09824186
申请日：2001-04-03
申请人： Yasuyuki Murakami , Shigezumi Matsui , Kunihiko Nishiyama , Atsushi Kiuchi , Yuichi Takitsune
发明人： Yasuyuki Murakami , Shigezumi Matsui , Kunihiko Nishiyama , Atsushi Kiuchi , Yuichi Takitsune
IPC分类号： G06F938
摘要： In order to simplify the instruction prefetch architecture for use with the programs having few loops, and having instructions almost in linear and sequential addresses, the bus controller in accordance with the present invention for controlling the bus in an external memory includes a plurality of instruction buffers, flags each specific to each of instruction buffers, and a buffer controller circuit. The buffer controller circuit may allocate one of specific values that plural lower bits of an instruction address may take to each of the instruction buffers, and prefetch instructions to the instruction buffers each corresponding to a respective addresses designated to by the plural lower bits, from the address following a predetermined fetch address. The constitution for instruction prefetch as above may be implemented in a simpler manner than the controlling structure using address tags of a cache memory or the controlling structure using read-write pointer based on the counter in FIFO buffers.

38. 发明授权

US5511178A Cache control system equipped with a loop lock indicator for indicating the presence and/or absence of an instruction in a feedback loop section 失效
标题翻译：缓存控制系统配备有用于指示反馈回路部分中存在和/或不存在指令的循环锁定指示器
公开(公告)号：US5511178A
公开(公告)日：1996-04-23
申请号：US156301
申请日：1993-11-23
申请人： Hiroshi Takeda , Shigezumi Matsui
发明人： Hiroshi Takeda , Shigezumi Matsui
IPC分类号： G06F9/38 , G06F9/45 , G06F12/08 , G06F12/12 , G06F12/02
CPC分类号： G06F9/381 , G06F12/0862 , G06F2212/6028
摘要： In a cache memory 20, there exist a plurality of cache lines 201, each of which is equipped with a loop lock L for indicating that an instruction is present in a feedback loop section. The states of the loop locks L are dynamically changed according to the executed state of a program. At the time of excluding the cache lines for a prefetch, the instruction string in the loop is held in the cache memory 20 till the program control transfers to the outside of the loop.
摘要翻译：在高速缓冲存储器20中，存在多个高速缓存线201，每条高速缓存线201配备有用于指示反馈回路部分中存在指令的回路锁L。循环锁L的状态根据程序的执行状态而动态变化。在排除用于预取的高速缓存行时，循环中的指令串被保存在高速缓冲存储器20中，直到程序控制转移到循环的外部。

39. 发明授权

US08386992B2 Data processing device 有权
标题翻译：数据处理装置
公开(公告)号：US08386992B2
公开(公告)日：2013-02-26
申请号：US13310217
申请日：2011-12-02
申请人： Takafumi Betsui , Naoto Taoka , Motoo Suwa , Shigezumi Matsui , Norihiko Sugita , Yoshiharu Fukushima
发明人： Takafumi Betsui , Naoto Taoka , Motoo Suwa , Shigezumi Matsui , Norihiko Sugita , Yoshiharu Fukushima
IPC分类号： G06F17/50
CPC分类号： G11C5/04 , G11C5/02 , G11C5/06 , G11C5/063 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L24/17 , H01L25/18 , H01L2224/16 , H01L2224/16227 , H01L2224/49175 , H01L2924/1432 , H01L2924/14361 , H01L2924/15311 , H01L2924/30107 , H01L2924/3011 , H05K1/0237 , H05K1/181 , H05K3/4602 , H05K2201/09236 , H05K2201/093 , H05K2201/09663 , H05K2201/10159 , H05K2201/10522 , H05K2201/10734 , Y02P70/611 , H01L2924/00
摘要： A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.
摘要翻译：设置在矩形半导体板上的微型计算机具有存储器接口电路。存储器接口电路分别设置在从作为基准位置的一个角部沿着半导体板的两侧的周边延伸的位置。在这种情况下，与仅在一侧具有存储器接口电路的半导体板相比，可以减小对半导体板的尺寸减小的限制。每个分离的存储器接口电路上的各个部分电路具有与数据和数据选通信号相关联的相等的数据单元。因此，微型计算机在主板和模块板上简化了线路设计。

40. 发明授权

US07961545B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07961545B2
公开(公告)日：2011-06-14
申请号：US12629981
申请日：2009-12-03
申请人： Masanao Yamaoka , Koichiro Ishibashi , Shigezumi Matsui , Kenichi Osada
发明人： Masanao Yamaoka , Koichiro Ishibashi , Shigezumi Matsui , Kenichi Osada
IPC分类号： G11C5/14
CPC分类号： G11C11/419 , G11C5/146 , G11C5/147 , G11C11/4125 , G11C11/417 , G11C2207/2227
摘要： A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
摘要翻译：系统LSI中的逻辑电路设置有电源开关，以便在待机时切断开关，从而减少漏电流。同时，系统LSI的SRAM电路控制衬底偏置以减少漏电流。

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