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31. 发明授权

US08290750B1 Signal detect for high-speed serial interface 有权
标题翻译：信号检测用于高速串行接口
公开(公告)号：US08290750B1
公开(公告)日：2012-10-16
申请号：US13036437
申请日：2011-02-28
申请人： Wilson Wong , Allen Chan , Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang , Weiqi Ding
发明人： Wilson Wong , Allen Chan , Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang , Weiqi Ding
IPC分类号： H03F1/26
CPC分类号： H03K5/19 , H03K19/1774 , H03K19/17744 , H03K19/1778
摘要： Signal detection circuitry for a serial interface oversamples the input—i.e., samples the input multiple times per clock cycle—so that the likelihood of missing a signal is reduced. Sampling may be done with a regenerative latch which has a large bandwidth and can latch a signal at high speed. The amplitude threshold for detection may be programmable, particularly in a programmable device. Thus, between the use of a regenerative latch which is likely to catch any signal that might be present, and the use of oversampling to avoid the problem of sampling at the wrong time, the likelihood of failing to detect a signal is greatly diminished. Logic, such as a state machine, may be used to determine whether the samples captured s do or do not represent a signal. That logic may be programmable, allowing a user to set various parameters for signal detection.
摘要翻译：串行接口的信号检测电路对输入进行过采样，即每个时钟周期对输入进行多次采样，从而减少信号丢失的可能性。可以使用具有大带宽的再生锁存器并且可以高速锁存信号来进行采样。用于检测的幅度阈值可以是可编程的，特别是在可编程器件中。因此，在可能捕获可能存在的任何信号的再生锁存器的使用之间以及使用过采样以避免在错误时间采样的问题，大大减少了不能检测信号的可能性。可以使用诸如状态机的逻辑来确定捕获的样本是否或不表示信号。该逻辑可以是可编程的，允许用户设置用于信号检测的各种参数。

32. 发明授权

US07860203B1 High-speed serial data signal interface architectures for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的高速串行数据信号接口架构
公开(公告)号：US07860203B1
公开(公告)日：2010-12-28
申请号：US11725653
申请日：2007-03-19
申请人： Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Thungoc M. Tran
发明人： Sergey Shumarayev , Wilson Wong , Tim Tri Hoang , Thungoc M. Tran
IPC分类号： H04L7/00
CPC分类号： H03L7/087 , H04J3/0688 , H04L7/033
摘要： A programmable logic device integrated circuit (“PLD”) includes high-speed serial interface (“HSSI”) circuitry in addition to programmable logic circuitry. The HSSI circuitry includes multiple channels of nominal data-handling circuitry (typically including clock and data recovery (“CDR”) circuitry), and at least one channel of nominal clock management unit (“CMU”) circuitry (typically including phase-locked loop (“PLL”) circuitry or the like). To increase the flexibility with which the channels can be used, the nominal data-handling channels are equipped to alternatively perform CMU-type functions, and the nominal CMU channel is equipped to alternatively perform data-handling functions.
摘要翻译：可编程逻辑器件集成电路（“PLD”）除了可编程逻辑电路之外还包括高速串行接口（“HSSI”）电路。 HSSI电路包括多个标称数据处理电路（通常包括时钟和数据恢复（“CDR”）电路）的通道，以及标称时钟管理单元（“CMU”）电路的至少一个通道（通常包括锁相环（“PLL”）电路等）。为了增加可以使用信道的灵活性，标称数据处理信道被配备为交替执行CMU类型功能，并且标称CMU信道被配备为备选地执行数据处理功能。

33. 发明授权

US07777526B2 Increased sensitivity and reduced offset variation in high data rate HSSI receiver 有权
标题翻译：在高数据速率HSSI接收机中增加灵敏度和减少偏移变化
公开(公告)号：US07777526B2
公开(公告)日：2010-08-17
申请号：US12134777
申请日：2008-06-06
申请人： Sergey Shumarayev , Thungoc M. Tran , Wilson Wong , Simardeep Maangat
发明人： Sergey Shumarayev , Thungoc M. Tran , Wilson Wong , Simardeep Maangat
IPC分类号： H03K19/094
CPC分类号： H03K19/018514 , H03F3/45197 , H03F2203/45494 , H03F2203/45686
摘要： Signal offset variation caused by transistor variation/mismatch in integrated circuits may be reduced. In one embodiment, a buffer circuit has variable-valued circuit elements. Offset variation measurements are made and the variable-valued circuit elements are calibrated to reduce the measured offset variation. In another embodiment, each amplifying stage of a multi-stage buffer provides variable gain. The total DC gain of the cascade is distributed unevenly across the stages, with more DC gain being provided by amplifier stages at the beginning of the cascade than at the end. An additional pre-amplifier stage can also be provided at the beginning of the cascade.
摘要翻译：集成电路中晶体管变化/失配引起的信号偏移变化可能会降低。在一个实施例中，缓冲电路具有可变值电路元件。进行偏移变化测量，并校准可变值电路元件以减少测量的偏移变化。在另一个实施例中，多级缓冲器的每个放大级提供可变增益。级联的总直流增益不均匀地分布在整个级中，在级联开始时比放大器级提供更多的直流增益。在级联开始时也可以提供一个额外的前级放大器级。

34. 发明授权

US07733982B2 Signal adjustment receiver circuitry 失效
标题翻译：信号调节接收器电路
公开(公告)号：US07733982B2
公开(公告)日：2010-06-08
申请号：US12511022
申请日：2009-07-28
申请人： Wilson Wong , Rakesh H. Patel , Sergey Shumarayev , Tin H. Lai
发明人： Wilson Wong , Rakesh H. Patel , Sergey Shumarayev , Tin H. Lai
IPC分类号： H03K9/00 , H04L27/00
CPC分类号： H04B7/005 , H04L25/03006 , H04L25/061
摘要： Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block.
摘要翻译：公开了一种用于调整从通信路径接收的信号的系统和方法。接收机可以接收来自衰减信号的至少一些频率分量的通信路径的信号。接收机可以包括调整接收信号的频率内容中的至少一些的均衡块，提供归一化信号幅度和/或归一化边沿斜率的信号归一化块以及控制块。在一个实施例中，控制块控制用于高频而不是低频的均衡块中的频率调整。对于低频调整，控制块控制信号归一化块中的归一化信号幅度。以这种方式，在信号归一化块中执行低频内容的受控调整。

35. 发明授权

US07697600B2 Programmable receiver equalization circuitry and methods 有权
标题翻译：可编程接收机均衡电路和方法
公开(公告)号：US07697600B2
公开(公告)日：2010-04-13
申请号：US11182658
申请日：2005-07-14
申请人： Simardeep Maangat , Sergey Shumarayev , Wilson Wong , ThuNgoc Tran
发明人： Simardeep Maangat , Sergey Shumarayev , Wilson Wong , ThuNgoc Tran
IPC分类号： H03H7/30
CPC分类号： H04L25/03885 , H04B3/04 , H04L25/03019
摘要： Data signals transmitted over transmission media suffer from attenuation caused by the transmission media. Equalization circuitry may be provided to compensate for attenuation caused by the transmission media. Equalization circuitry may include multiple stages arranged in series to allow the frequency responses of the stages to aggregate together. Each stage may be programmable to insert a zero, which causes the frequency response of the stage to increase in magnitude by 20 dB/decade. The frequency location of the zero may also be programmable to allow each stage to contribute a certain amount of gain for a specific frequency. Each stage may also be programmable to determine the location of poles for reduction of high frequency noise and cross-talk cancellation.
摘要翻译：通过传输介质传输的数据信号遭受由传输介质引起的衰减。可以提供均衡电路以补偿由传输介质引起的衰减。均衡电路可以包括串联布置的多个级，以允许级的频率响应聚合在一起。每个级可以是可编程的，以插入一个零，这使得该级的频率响应在幅度上增加20dB /十倍。零的频率位置也可以是可编程的，以允许每个级对特定频率贡献一定量的增益。每个阶段也可以被编程以确定用于降低高频噪声和串扰取消的极点的位置。

36. 发明授权

US07675326B1 Dynamically-adjustable differential output drivers 失效
标题翻译：动态可调差分输出驱动器
公开(公告)号：US07675326B1
公开(公告)日：2010-03-09
申请号：US12163709
申请日：2008-06-27
申请人： Mei Luo , Sergey Shumarayev , Wilson Wong , Chong H. Lee
发明人： Mei Luo , Sergey Shumarayev , Wilson Wong , Chong H. Lee
IPC分类号： H03K19/094
CPC分类号： H03K19/00369 , H03K19/01812 , H03K19/01837 , H03K19/018514 , H03K19/018585
摘要： Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuits. The peak-to-peak output voltage and common-mode voltage of the output drivers may be adjusted. Dynamic control circuitry may be used to control the settings of current sources, programmable resistors, and voltage source circuitry in the adjustable differential output driver automatically in real time. The adjustable components in the differential output driver may be adjusted by the dynamic control circuitry based on feedback information received from the integrated circuit to which the data is transmitted.
摘要翻译：使用动态可调差分输出驱动器提供系统和方法。诸如可编程逻辑器件的集成电路可以设置有用于将高速数据传输到其他集成电路的可调差分输出驱动器。可以调整输出驱动器的峰峰值输出电压和共模电压。动态控制电路可用于实时自动控制可调差分输出驱动器中的电流源，可编程电阻和电压源电路的设置。基于从发送数据的集成电路接收到的反馈信息，可以通过动态控制电路来调整差分输出驱动器中的可调节部件。

37. 发明授权

US07616657B2 Heterogeneous transceiver architecture for wide range programmability of programmable logic devices 有权
标题翻译：异构收发器架构，用于可编程逻辑器件的广泛可编程性
公开(公告)号：US07616657B2
公开(公告)日：2009-11-10
申请号：US11402417
申请日：2006-04-11
申请人： Sergey Shumarayev , Bill W Bereza , Chong H Lee , Rakesh H Patel , Wilson Wong
发明人： Sergey Shumarayev , Bill W Bereza , Chong H Lee , Rakesh H Patel , Wilson Wong
IPC分类号： H04J3/00
CPC分类号： H04L5/14 , H03K19/17744 , H04L27/00
摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.
摘要翻译：可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道达到第二个相对较高的最大数据速率。相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

38. 发明授权

US07602212B1 Flexible high-speed serial interface architectures for programmable integrated circuit devices 有权
标题翻译：用于可编程集成电路器件的灵活的高速串行接口架构
公开(公告)号：US07602212B1
公开(公告)日：2009-10-13
申请号：US11904003
申请日：2007-09-24
申请人： Allen Chan , Sergey Shumarayev , Wilson Wong
发明人： Allen Chan , Sergey Shumarayev , Wilson Wong
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/17736 , H03K19/17732 , H03K19/17744
摘要： An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes high-speed serial data signal interface channels, some of which include more circuitry that is dedicated to performing various high-speed serial interface functions than others of those channels have. To increase the flexibility with which such circuitry in a more feature-rich channel can be used, routing is provided for selectively allowing a less feature-rich channel to use certain dedicated circuitry of a more feature-rich channel that is not itself using all of its dedicated circuitry.
摘要翻译：集成电路（例如，可编程集成电路，例如可编程微控制器，可编程逻辑器件等）包括高速串行数据信号接口通道，其中一些包括更多专用于执行各种高速串行数据接口功能比其他那些通道有。为了增加可以使用更多功能丰富的信道中的这种电路的灵活性，提供路由选择性地允许较不富有特征的信道使用更多功能丰富的信道的某些专用电路，其不是本身使用全部其专用电路。

39. 发明申请

US20090154591A1 High-speed serial data signal transmitter driver circuitry 审中-公开
标题翻译：高速串行数据信号发射器驱动电路
公开(公告)号：US20090154591A1
公开(公告)日：2009-06-18
申请号：US12002540
申请日：2007-12-17
申请人： Wilson Wong , Allen Chan , Sergey Shumarayev , Weiqi Ding
发明人： Wilson Wong , Allen Chan , Sergey Shumarayev , Weiqi Ding
IPC分类号： H04L27/00
CPC分类号： H04L25/028
摘要： Transmitter driver circuitry for outputting a high-speed serial data signal (e.g., in the range of about 10 gigabits per second or higher) includes H-tree driver circuitry having only a main driver stage and a post-tap driver stage. At least one transistor in the H-tree driver circuitry is constructed and connected to provide electrostatic discharge protection. PMOS and NMOS current sources are used for the H-tree driver circuitry to enhance power supply noise rejection.
摘要翻译：用于输出高速串行数据信号（例如，在大约10吉比特每秒或更高的范围内）的发射器驱动器电路包括仅具有主驱动器级和抽头后驱动级的H树驱动器电路。 H树驱动器电路中的至少一个晶体管被构造和连接以提供静电放电保护。 PMOS和NMOS电流源用于H-tree驱动器电路，以增强电源噪声抑制。

40. 发明申请

US20090154542A1 High-speed serial data signal receiver circuitry 有权
标题翻译：高速串行数据信号接收电路
公开(公告)号：US20090154542A1
公开(公告)日：2009-06-18
申请号：US12002539
申请日：2007-12-17
申请人： Weiqi Ding , Mengchi Liu , Wilson Wong , Sergey Shumarayev
发明人： Weiqi Ding , Mengchi Liu , Wilson Wong , Sergey Shumarayev
IPC分类号： H03H7/30
CPC分类号： H04L25/03885 , H04L7/0054 , H04L25/03019 , H04L25/03878
摘要： Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gpbs and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.
摘要翻译：用于接收高速串行数据信号（例如，具有在约10Gpbs及更高的范围内的比特率）的电路包括仅具有两个串联连接级的两级连续时间线性均衡器。可以提供相位检测器电路用于接收均衡器的串行输出，并将该输出中的连续比特对转换为连续并行形式的位对。可以提供进一步的解复用电路以将并行形式位对的连续组分解成最终并行位组，在位数（例如，64个并行位）方面可能相当大。本发明的另一方面涉及用于从相对大的并行数据比特组相对于高速串行数据输出信号有效地进行反向的多路复用器电路。

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