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31. 发明授权

US07781832B2 Trench-type power MOS transistor and integrated circuit utilizing the same 有权
标题翻译：沟槽型功率MOS晶体管和利用其的集成电路
公开(公告)号：US07781832B2
公开(公告)日：2010-08-24
申请号：US12128452
申请日：2008-05-28
申请人： Ming Tang , Shih-Ping Chiao
发明人： Ming Tang , Shih-Ping Chiao
IPC分类号： H01L29/732
CPC分类号： H01L29/7825 , H01L29/0653 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/4236 , H01L29/42368 , H01L29/7809
摘要： A power MOS transistor comprises a drain region, a trench gate, a source region, a well region, a deep well region and a substrate region. The drain region has a doping region of a first conductivity type connected to a drain electrode. The trench gate has an insulating layer and extends into the drain region. The source region has a doping region of the first conductivity type connected to a source electrode. The well region is doped with a second conductivity type, formed under the source region, and connected to the source electrode. The deep well region is doped with the first conductivity type and is formed under the drain region and the well region. The substrate region is doped with the second conductivity type and is formed under the deep well region. The drain region is formed at one side of the trench gate and the source region is formed at the opposing side of the trench gate such that the trench gate laterally connects the source region and the drain region.
摘要翻译：功率MOS晶体管包括漏区，沟槽栅，源极区，阱区，深阱区和衬底区。漏极区域具有连接到漏电极的第一导电类型的掺杂区域。沟槽栅极具有绝缘层并延伸到漏极区域中。源极区域具有连接到源电极的第一导电类型的掺杂区域。阱区掺杂有第二导电类型，形成在源极区下方，并连接到源电极。深阱区域掺杂有第一导电类型并形成在漏极区域和阱区域之下。衬底区域掺杂有第二导电类型并形成在深阱区域下方。漏极区域形成在沟槽栅极的一侧，并且源极区域形成在沟槽栅极的相对侧，使得沟槽栅极横向地连接源极区域和漏极区域。

32. 发明申请

US20080265311A1 VERTICAL TRANSISTOR AND METHOD FOR PREPARING THE SAME 审中-公开
标题翻译：垂直晶体管及其制备方法
公开(公告)号：US20080265311A1
公开(公告)日：2008-10-30
申请号：US11756529
申请日：2007-05-31
申请人： Ming Tang , Frank Chen
发明人： Ming Tang , Frank Chen
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/0657 , H01L21/3086 , H01L29/1037 , H01L29/66636 , H01L29/78
摘要： A vertical transistor comprises a substrate having a step structure, two doped regions positioned in the substrate at the two sides of the step structure, and a carrier channel positioned in the substrate between the two doped regions, wherein the step structure includes an inclined edge and the width of the carrier channel at the inclined edge is larger than the width of the doped regions. The step structure comprises two non-rectangular surfaces, such as the trapezoid or triangular surfaces, and a rectangular surface. The non-rectangular surfaces connect to the doped regions, and the rectangular surface is perpendicular to the non-rectangular surface.
摘要翻译：垂直晶体管包括具有阶梯结构的衬底，位于阶梯结构两侧的衬底中的两个掺杂区域和位于两个掺杂区域之间的衬底中的载流子通道，其中阶梯结构包括倾斜边缘和倾斜边缘处的载流子通道的宽度大于掺杂区域的宽度。台阶结构包括两个非矩形表面，例如梯形或三角形表面，以及矩形表面。非矩形表面连接到掺杂区域，矩形表面垂直于非矩形表面。

33. 发明申请

US20050275006A1 [MULTI-GATE DRAM WITH DEEP-TRENCH CAPACITOR AND FABRICATION THEREOF] 审中-公开
标题翻译： [具有深度电容器及其制造的多栅极DRAM]
公开(公告)号：US20050275006A1
公开(公告)日：2005-12-15
申请号：US10709719
申请日：2004-05-25
申请人： Ming Tang
发明人： Ming Tang
IPC分类号： H01L21/20 , H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10867 , H01L27/10876 , H01L27/10885 , H01L27/10891
摘要： A multi-gate DRAM cell is described, including a multi-gate transistor and a deep trench capacitor. The transistor includes a semiconductor pillar, a multi-gate, a gate dielectric layer, a first and a second source/drain regions. The pillar is beside the deep trench capacitor not overlapping with the latter. The multi-gate is at least on three sidewalls of the pillar separated by the gate dielectric layer, and can be a treble gate or a surrounding gate. The first source/drain region is in the top portion of the pillar, and the second source/drain region in the pillar coupling with the deep trench capacitor.
摘要翻译：描述了多栅极DRAM单元，包括多栅极晶体管和深沟槽电容器。晶体管包括半导体柱，多栅极，栅极电介质层，第一和第二源极/漏极区域。支柱位于深沟槽电容器旁边，与后者不重叠。多栅极至少在由栅极介电层分隔的柱的三个侧壁上，并且可以是高音门或周围栅极。第一源/漏区位于柱的顶部，并且与第二沟槽电容器耦合的柱中的第二源极/漏极区。

34. 发明授权

US06775717B1 Method and apparatus for reducing latency due to set up time between DMA transfers 有权
标题翻译：由于DMA传输之间建立时间而减少延迟的方法和装置
公开(公告)号：US06775717B1
公开(公告)日：2004-08-10
申请号：US10177382
申请日：2002-06-21
申请人： Ming Tang , Jiann Liao
发明人： Ming Tang , Jiann Liao
IPC分类号： G06F300
CPC分类号： G06F13/28
摘要： A method and apparatus for reducing latency due to set up time between DMA transfers are described. The method comprises initiating arbitration of DMA channel requests prior to completion of a current DMA transfer; and initiating set up for a next DMA transfer prior to completion of the current DMA transfer according to the arbitration. One implementation of the apparatus includes one or more DMA channel interfaces providing a series of DMA channel requests such that a DMA channel request for a next DMA transfer is provided before a current DMA transfer is completed; and a DMA controller that initiates arbitration of DMA channel requests after they are provided by the one or more DMA channel interfaces and before the current DMA transfer is completed, and initiates set up for the next DMA transfer prior to completion of the current DMA transfer according to the arbitration.
摘要翻译：描述了由于DMA传输之间建立时间而减少等待时间的方法和装置。该方法包括在完成当前DMA传输之前启动DMA通道请求的仲裁; 并根据仲裁在当前DMA传输完成之前启动设置以进行下一个DMA传输。该装置的一个实现包括一个或多个DMA通道接口，提供一系列DMA通道请求，使得在当前DMA传输完成之前提供用于下一个DMA传输的DMA通道请求; 以及DMA控制器，在由DMA通道接口提供DMA通道接口之后并在当前DMA传输完成之前启动DMA通道请求仲裁，并且在完成当前DMA传输之前启动对下一次DMA传输的设置，仲裁。

35. 发明授权

US09742947B2 Image reading apparatus 有权
公开(公告)号：US09742947B2
公开(公告)日：2017-08-22
申请号：US13662205
申请日：2012-10-26
申请人： Ming Tang
发明人： Ming Tang
IPC分类号： H04N1/04 , H04N1/00 , H04N1/193 , H04N1/028 , H04N1/10 , H04N1/12
CPC分类号： H04N1/00909 , H04N1/00981 , H04N1/02865 , H04N1/1013 , H04N1/1235 , H04N1/193 , H04N2201/0094
摘要： An image reading apparatus includes an LED light source, a CCD sensor receiving light reflected from a document irradiated with light from the LED light source, a fan, and a frame housing the LED light source, the CCD sensor and the fan. The fan circulates air in a substantially sealed space formed by the frame. Thus, temperature difference in the image reading apparatus can be reduced while not degrading dust-proof property of the apparatus, and efficient heat radiation to the outside becomes possible. Thus, variation of sensitivity of CCD sensor, deviation of point of focus of image forming system and deviation of reading position caused by temperature increase can be prevented.

36. 发明授权

US08299526B2 Integrated circuit utilizing trench-type power MOS transistor 有权
标题翻译：利用沟槽型功率MOS晶体管的集成电路
公开(公告)号：US08299526B2
公开(公告)日：2012-10-30
申请号：US12838145
申请日：2010-07-16
申请人： Ming Tang , Shih-Ping Chiao
发明人： Ming Tang , Shih-Ping Chiao
IPC分类号： H01L29/78
CPC分类号： H01L29/7825 , H01L29/0653 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/4236 , H01L29/42368 , H01L29/7809
摘要： An integrated circuit includes a power MOS transistor which comprises a drain region, a trench gate, a source region, a well region, a deep well region and a substrate region. The drain region has a doping region of a first conductivity type connected to a drain electrode. The trench gate has an insulating layer and extends into the drain region. The source region has a doping region of the first conductivity type connected to a source electrode. The well region is doped with a second conductivity type, formed under the source region, and connected to the source electrode. The deep well region is doped with the first conductivity type and is formed under the drain region and the well region. The substrate region is doped with the second conductivity type and is formed under the deep well region. The drain region is formed at one side of the trench gate and the source region is formed at the opposing side of the trench gate such that the trench gate laterally connects the source region and the drain region.
摘要翻译：集成电路包括功率MOS晶体管，其包括漏极区，沟槽栅极，源极区域，阱区域，深阱区域和衬底区域。漏极区域具有连接到漏电极的第一导电类型的掺杂区域。沟槽栅极具有绝缘层并延伸到漏极区域中。源极区域具有连接到源电极的第一导电类型的掺杂区域。阱区掺杂有第二导电类型，形成在源极区下方，并连接到源电极。深阱区域掺杂有第一导电类型并形成在漏极区域和阱区域之下。衬底区域掺杂有第二导电类型并形成在深阱区域下方。漏极区域形成在沟槽栅极的一侧，并且源极区域形成在沟槽栅极的相对侧，使得沟槽栅极横向地连接源极区域和漏极区域。

37. 发明授权

US08134205B2 Layout structure of power MOS transistor 有权
标题翻译：功率MOS晶体管的布局结构
公开(公告)号：US08134205B2
公开(公告)日：2012-03-13
申请号：US12683053
申请日：2010-01-06
申请人： Ming Tang , Shih-Ping Chiao
发明人： Ming Tang , Shih-Ping Chiao
IPC分类号： H01L29/66 , H01L21/336
CPC分类号： H01L29/0696 , H01L29/4238 , H01L29/78 , H01L29/7809 , H01L29/7816 , H01L29/7835
摘要： The present invention discloses a layout structure of a transistor unit of a power MOS transistor, wherein the layout structure comprises a drain area, a plurality of body areas, a plurality of source areas and a gate area. The plurality of body areas surround the drain area. The plurality of source areas extend from the perimeters of the plurality of body areas in an anisotropic manner. The gate area is disposed between the drain area and the plurality of source areas. The contacts of the drain area, the plurality of body areas and the plurality of source areas are all disposed on the same side of the layout structure.
摘要翻译：本发明公开了功率MOS晶体管的晶体管单元的布局结构，其中布局结构包括漏极区域，多个体区域，多个源极区域和栅极区域。多个身体区域围绕排水区域。多个源区域以各向异性方式从多个身体区域的周边延伸。栅极区域设置在漏极区域和多个源极区域之间。排水区域，多个主体区域和多个源区域的触点都布置在布局结构的同一侧。

38. 发明申请

US20110021402A1 Detergent Composition 审中-公开
标题翻译：洗涤剂组合物
公开(公告)号：US20110021402A1
公开(公告)日：2011-01-27
申请号：US12895963
申请日：2010-10-01
申请人： Ming Tang , Hiroshi Oh , Sen Liu , Victor Manuel Arredondo
发明人： Ming Tang , Hiroshi Oh , Sen Liu , Victor Manuel Arredondo
IPC分类号： C11D7/32 , C07C309/04 , C07C317/04 , C07F9/09
CPC分类号： C11D3/30 , C11D1/02
摘要： A solid detergent composition having the salt of an anionic surfactant and of a monopropanolamine counterion.
摘要翻译：具有阴离子表面活性剂盐和单丙醇胺抗衡离子的固体洗涤剂组合物。

39. 发明申请

US20090143269A1 Detergent Composition 失效
标题翻译：洗涤剂组合物
公开(公告)号：US20090143269A1
公开(公告)日：2009-06-04
申请号：US12276638
申请日：2008-11-24
申请人： Junhua Du , Qing Chen , Li Ran , Ignacio Gallo-Perez , Ming Tang , Kenneth Nathan Price
发明人： Junhua Du , Qing Chen , Li Ran , Ignacio Gallo-Perez , Ming Tang , Kenneth Nathan Price
IPC分类号： C11D3/36
CPC分类号： C11D3/06
摘要： A detergent composition comprising: from 0.01% to 90% by weight of a surfactant system, one or more detergency builder(s), comprising a phosphate builder, and the phosphate builder containing pyrophosphate, wherein the composition comprises at most 12% by weight of phosphate builder(s) and the phosphate builder(s) comprise(s) at least 40% by weight of pyrophosphate(s)
摘要翻译：一种洗涤剂组合物，其包含：0.01重量％至90重量％的表面活性剂体系，一种或多种洗涤助洗剂，其包含磷酸盐助洗剂和含有焦磷酸盐的磷酸盐助洗剂，其中所述组合物包含至多12重量％磷酸盐助洗剂和磷酸盐助洗剂包含至少40重量％的焦磷酸盐，

40. 发明授权

US07386774B1 Memory unit with controller managing memory access through JTAG and CPU interfaces 有权
标题翻译：带控制器的存储单元通过JTAG和CPU接口管理存储器访问
公开(公告)号：US07386774B1
公开(公告)日：2008-06-10
申请号：US10788943
申请日：2004-02-26
申请人： Mitrajit Chatterjee , Ming Tang , Peter Z. Onufryk , Steven Chau
发明人： Mitrajit Chatterjee , Ming Tang , Peter Z. Onufryk , Steven Chau
IPC分类号： G01R31/28
CPC分类号： G06F21/575 , G06F21/79 , G06F2221/2105
摘要： A memory unit includes a memory organized into protected and non-protected areas. A controller manages access to the memory so that the protected area can be written to through a JTAG or CPU interface. Once written to, the protected area is only accessible to particular logic and cannot be over-written until the entire memory is erased. The controller is configured to allow a BCV to be stored in the memory through either the JTAG or CPU interface. The controller is also configured to allow writing to the protected area and boot configuration vector in memory before CPU boot-up by using a JTAG clock signal provided through an external pin when a system clock signal is not available. A reset circuit generates one or more initialization signals using either the BCV from memory or another BCV provided on external BCV pins, depending upon whether another external BCV pin is asserted.
摘要翻译：存储器单元包括组织成受保护区域和非保护区域的存储器。控制器管理对存储器的访问，以便可以通过JTAG或CPU接口写保护区。一旦写入，保护区只能访问特定的逻辑，并且不能被覆盖，直到整个内存被擦除。控制器配置为允许通过JTAG或CPU接口将BCV存储在存储器中。控制器还配置为在系统时钟信号不可用时，通过使用通过外部引脚提供的JTAG时钟信号，在CPU启动之前，将写入保护区域并启动存储器中的配置向量。复位电路使用来自存储器的BCV或外部BCV引脚上提供的另一个BCV产生一个或多个初始化信号，这取决于是否断言另一个外部BCV引脚。

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