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    • 31. 发明授权
    • Cyclic redundancy check generating circuit
    • 循环冗余校验生成电路
    • US07328396B2
    • 2008-02-05
    • US10709794
    • 2004-05-28
    • Gregory J. Mann
    • Gregory J. Mann
    • H03M13/00
    • H03M13/091H03M13/6572
    • A circuit, a method, and a method of designing the circuit, the circuit including: multiple W-bit packet data slice latches; a data partition comprising multiple data XOR subtree levels and having data latches between the data XOR subtree levels; a remainder partition comprising multiple remainder XOR subtree levels and having remainder latches between the remainder XOR subtree levels; a combinatorial XOR tree, outputs of the remainder partition and outputs of the data partition connected to inputs of the combinatorial XOR tree; and a remainder latch, combinatorial XOR tree connected to the remainder latch and the outputs of the remainder latch connected to the remainder partition.
    • 一种设计电路的电路,方法和方法,所述电路包括:多个W位分组数据片锁存器; 数据分区,包括多个数据XOR子树级别,并且在数据XOR子树级之间具有数据锁存器; 剩余分区包括多个余数XOR子树级别,并且在余数XOR子树级别之间具有余数锁存器; 组合XOR树,连续到组合XOR树的输入的数据分区的剩余分区和输出的输出; 以及连接到剩余锁存器的剩余锁存组合XOR树,并且剩余锁存器的输出连接到其余分区。