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31. 发明申请

US20070075736A1 FPGA powerup to known functional state 失效
公开(公告)号：US20070075736A1
公开(公告)日：2007-04-05
申请号：US11371833
申请日：2006-03-09
申请人： Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Jack Smith , Sebastian Ventrone , Keith Williams
发明人： Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Jack Smith , Sebastian Ventrone , Keith Williams
IPC分类号： H03K19/177
CPC分类号： H03K19/177
摘要： A field programmable gate array (FPGA) device including a non-programming-based default power-on electronic configuration. The non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronous set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.

32. 发明申请

US20060189294A1 Wireless communication system within a system on a chip 有权
标题翻译：芯片内系统内的无线通信系统
公开(公告)号：US20060189294A1
公开(公告)日：2006-08-24
申请号：US11410829
申请日：2006-04-24
申请人： Kenneth Goodnow , Riyon Harding , Charles Masenas , Jason Norman , Sebastian Ventrone
发明人： Kenneth Goodnow , Riyon Harding , Charles Masenas , Jason Norman , Sebastian Ventrone
IPC分类号： H04B1/28
CPC分类号： H04B1/38
摘要： A communication system for transmitting data between cores embedded in an integrated circuit on a silicon chip. Communication system includes transmitter circuitry for wirelessly transmitting data between cores and receiver circuitry for wirelessly receiving the transmission of data from other cores. Both transmitter circuitry and receiver circuitry may include of a phase-locked loop circuit having a voltage-controlled oscillator. Each core may transmit and receive data on a unique frequency with respect to other cores embedded in an integrated circuit on a silicon chip or transmit and receive data on the same frequency as other cores embedded in an integrated circuit on a silicon chip. Groups of cores may share transmitter and receiver circuitry.
摘要翻译：一种用于在嵌入在硅芯片上的集成电路中的核之间传输数据的通信系统。通信系统包括用于在核心和接收机电路之间无线地传输数据的发射机电路，用于无线地接收来自其他核的数据传输。发射机电路和接收机电路都可以包括具有压控振荡器的锁相环电路。每个核心可以相对于嵌入在硅芯片上的集成电路中的其它核心以独特的频率发送和接收数据，或者以与嵌入在硅芯片上的集成电路中的其它芯片相同的频率发送和接收数据。核心组可以共享发射机和接收机电路。

33. 发明申请

US20050125760A1 Data processing in digital systems 失效
标题翻译：数字系统中的数据处理
公开(公告)号：US20050125760A1
公开(公告)日：2005-06-09
申请号：US10729750
申请日：2003-12-04
申请人： Kenneth Goodnow , Clarence Ogilvie , Sebastian Ventrone
发明人： Kenneth Goodnow , Clarence Ogilvie , Sebastian Ventrone
IPC分类号： G06F15/177 , G06F15/78 , G06F17/50 , H01L25/00 , H03K19/177
CPC分类号： G06F17/5054 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： A structure comprising an FPGA (Field-Programmable Gate Array) for relieving bottlenecks, and a method for operating the structure. The FPGA comprises multiple FPGA elements each of which includes a CLB (Configurable Logic Block), an instruction queue, and a data buffer. One functional block after another (separate from one another) can be formed in the FPGA via a first local IO (Input/Output) circuit and moved to a second local IO circuit. Within each functional block, a mapped logic location function calculates the direction, distance, and the time for the step from the current location of the functional block stored in a mapped location register, and the destination stored in a mapped destination register, and the time allowed for the movement, and stores the direction and distance of the step in the mapped movement register. Then, the functional block moves according the direction and distance stored in the mapped movement register.
摘要翻译：包括用于缓解瓶颈的FPGA（现场可编程门阵列）的结构以及用于操作该结构的方法。 FPGA包括多个FPGA元件，每个FPGA元件包括CLB（可配置逻辑块），指令队列和数据缓冲器。可以通过第一本地IO（输入/输出）电路在FPGA中形成一个功能块（彼此分开）并移动到第二个本地IO电路。在每个功能块内，映射的逻辑位置函数计算从存储在映射位置寄存器中的功能块的当前位置以及存储在映射的目的地寄存器中的目的地的步长的方向，距离和时间，以及时间允许移动，并将步进的方向和距离存储在映射运动寄存器中。然后，功能块根据存储在映射运动寄存器中的方向和距离移动。

34. 发明申请

US20050071575A1 SEMICONDUCTOR DEVICE COMPRISING A PLURALITY OF MEMORY STRUCTURES 失效
标题翻译：包含大量存储器结构的半导体器件
公开(公告)号：US20050071575A1
公开(公告)日：2005-03-31
申请号：US10605366
申请日：2003-09-25
申请人： Kenneth Goodnow , Francis Kampf , Jason Norman , Sebastian Ventrone
发明人： Kenneth Goodnow , Francis Kampf , Jason Norman , Sebastian Ventrone
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0284
摘要： A structure and associated method of transfer data on a semiconductor device, comprising: a plurality of systems within the semiconductor device. Each system comprises at least one processing device and a local memory structure. Each processing device is electrically coupled to each local memory structure within each system. Each local memory structure is electrically coupled to each of the other said local memory structures. Each local memory structure is adapted to share address space with each of the processing devices. Each processing device is adapted to transmit data and instructions to each local memory structure.
摘要翻译：一种半导体器件上传输数据的结构和相关方法，包括：半导体器件内的多个系统。每个系统包括至少一个处理设备和本地存储器结构。每个处理设备电耦合到每个系统内的每个本地存储器结构。每个本地存储器结构电耦合到每个其他所述本地存储器结构。每个本地存储器结构适于与每个处理设备共享地址空间。每个处理设备适于将数据和指令传送到每个本地存储器结构。

35. 发明申请

US20050041448A1 POWER DOWN PROCESSING ISLANDS 失效
标题翻译：断电处理岛
公开(公告)号：US20050041448A1
公开(公告)日：2005-02-24
申请号：US10604328
申请日：2003-07-11
申请人： Rafael Blanco , John Cohn , Kenneth Goodnow , Douglas Stout , Sebastian Ventrone
发明人： Rafael Blanco , John Cohn , Kenneth Goodnow , Douglas Stout , Sebastian Ventrone
IPC分类号： G11C19/08 , H01L20060101
CPC分类号： G06F1/3203 , G06F1/3287 , G11C5/144 , G11C5/147 , G11C2207/2227 , Y02D10/171
摘要： A structure and associated method of processing data on a semi-conductor device comprising an input island, a processing island, and an output island formed on the semiconductor device. The input island is adapted to accept a specified amount of data and enable a means for providing a first specified voltage for powering the processing island after accepting the specified amount of data. The processing island is adapted to receive and process the specified amount of data from the input island upon powering the processing island by the first specified voltage. The output island is adapted to be powered by a second specified voltage. The processing island is further adapted to transmit the processed data to the output island upon said powering by the second specified voltage. The first specified voltage is adapted to be disabled thereby removing power from processing island upon completion of transmission of the processed data to the output island.
摘要翻译：一种在半导体器件上处理数据的结构和相关方法，包括形成在半导体器件上的输入岛，处理岛和输出岛。输入岛适于接收指定数量的数据，并且能够在接受指定数量的数据之后启用用于提供用于为处理岛供电的第一指定电压的装置。处理岛适于在对处理岛供电第一指定电压时从输入岛接收和处理指定量的数据。输出岛适于由第二规定电压供电。处理岛还适于在所述第二规定电压的供电时将经处理的数据发送到输出岛。第一指定电压适于被禁用，从而在完成将处理的数据传输到输出岛时从处理岛去除功率。

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