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    • 31. 发明授权
    • ITLDD transistor having variable work function and method for
fabricating the same
    • 具有可变功函数的ITLDD晶体管及其制造方法
    • US5061647A
    • 1991-10-29
    • US597946
    • 1990-10-12
    • Scott S. RothCarlos A. MazureKent J. CooperWayne J. RayMichael P. WooJung-Hui Lin
    • Scott S. RothCarlos A. MazureKent J. CooperWayne J. RayMichael P. WooJung-Hui Lin
    • H01L21/28H01L21/336H01L29/423H01L29/49H01L29/78
    • H01L29/6659H01L21/28114H01L29/42376H01L29/4983H01L29/7836
    • A semiconductor device and process wherein an ITLDD device (60) is formed having an inverse-T (IT) transistor gate with a variable work function (.PHI.) across the gate. The variable work function is attained by depositing a work function adjusting layer onto the thin gate extensions of the IT-gate. In accordance with one embodiment of the invention, a semiconductor substrate (10) of a first conductivity type is provided having a gate dielectric layer (12) formed thereon. First and second lightly doped regions (36, 37) of a second conductivity type are formed in the substrate which are spaced apart by a channel region (38). An IT-gate electrode (48) is formed on the gate dielectric layer overlying the first and second lightly doped regions and the channel region. The IT-gate has a relatively thick central section (32) and relatively thin lateral extensions (50) projecting from the central portion along the gate dielectric layer. A work function adjusting layer (46) overlies and is in intimate contact with at least the lateral extensions of the IT-gate. The presence of the work function adjusting layer changes the electrical characteristics of the extensions relative to the central section of the IT-gate. Heavily doped source and drain regions (52, 53) of the second conductivity type are formed in the substrate adjacent to the first and second lightly doped regions and aligned to the edge of the gate extensions.
    • 一种半导体器件和工艺,其中ITLDD器件(60)形成为具有跨越栅极的具有可变功函数(PHI)的逆T(IT)晶体管栅极。 可变功函数是通过将工作功能调整层沉积到IT门的薄门延伸上来实现的。 根据本发明的一个实施例,提供具有形成在其上的栅介电层(12)的第一导电类型的半导体衬底(10)。 第二导电类型的第一和第二轻掺杂区域(36,37)形成在衬底中,其被沟道区域(38)隔开。 在覆盖第一和第二轻掺杂区域和沟道区域的栅极电介质层上形成IT栅电极(48)。 IT门具有相对较厚的中心部分(32)和相对较薄的横向延伸部分(50),从中心部分沿着栅极介电层突出。 工作功能调整层(46)覆盖至少与IT门的侧向延伸部紧密接触。 工作功能调整层的存在改变了延伸部分相对于IT门的中心部分的电气特性。 第二导电类型的重掺杂源极和漏极区域(52,53)形成在与第一和第二轻掺杂区域相邻的衬底中,并且与栅极延伸部分的边缘对准。