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    • 34. 发明申请
    • Display panel and display apparatus having the same
    • 显示面板和具有该显示面板的显示装置
    • US20090073138A1
    • 2009-03-19
    • US12221329
    • 2008-08-01
    • Myung-Woo LeeHyung-Guel KimKee-Han UhSoo-Guy Rho
    • Myung-Woo LeeHyung-Guel KimKee-Han UhSoo-Guy Rho
    • G06F3/041
    • G06F3/0412
    • A display panel having a touch screen, the display panel includes an array substrate having a plurality of pixels and an opposite substrate having a plurality of touch electrodes. The array substrate includes the pixels receiving a data signal through thin film transistors and sensors electrically and physically making contact with the touch electrodes in response to an external pressure. Each sensor generates a common voltage input through the touch electrode in response to a scan signal controlling the thin film transistor as a sensing signal. Based on the generated sensing signal, a location coordinate to which the external pressure is applied is calculated, so that the number of wires for the display panel may decrease.
    • 一种具有触摸屏的显示面板,显示面板包括具有多个像素的阵列基板和具有多个触摸电极的相对基板。 阵列基板包括通过薄膜晶体管接收数据信号的像素和响应于外部压力与触摸电极电接触和物理接触的传感器。 每个传感器响应于控制薄膜晶体管作为感测信号的扫描信号,通过触摸电极产生公共电压输入。 基于产生的感测信号,计算施加外部压力的位置坐标,使得显示面板的线数可能减少。
    • 36. 发明申请
    • Parity signal generator
    • 奇偶校验信号发生器
    • US20060150068A1
    • 2006-07-06
    • US11320831
    • 2005-12-30
    • Moon-Seok YangMyung-Woo Lee
    • Moon-Seok YangMyung-Woo Lee
    • G06F11/00H03M13/00
    • G09G3/3685G09G3/3614
    • Provided is a parity signal generator for generating a parity signal by continuously detecting a horizontal sync signal. The parity signal generator includes a first detecting unit for generating a first detection signal by detecting whether the number of a horizontal sync signal is odd or even during an activation of a vertical sync signal; a second detecting unit for generating a second detection signal by detecting whether the number of the horizontal sync signal is odd or even during an inactivation of the vertical sync signal; and an output unit for receiving the first and second detection signals to output a parity signal.
    • 提供了一种用于通过连续检测水平同步信号来生成奇偶校验信号的奇偶校验信号发生器。 奇偶信号发生器包括:第一检测单元,用于通过在激活垂直同步信号期间检测水平同步信号的数量是奇数还是偶数来产生第一检测信号; 第二检测单元,用于通过在垂直同步信号的失活期间检测水平同步信号的数量是奇数还是偶数来产生第二检测信号; 以及输出单元,用于接收第一和第二检测信号以输出奇偶校验信号。
    • 37. 发明授权
    • Hot-plug of PCI bus using single chip
    • 使用单芯片的PCI总线热插拔
    • US06253267B1
    • 2001-06-26
    • US09126601
    • 1998-07-31
    • Hyung-Sun KimIn-Ho LeeHo-Kyu SonMyung-Jae GilMyung-Woo LeeSeung-Wha Yoo
    • Hyung-Sun KimIn-Ho LeeHo-Kyu SonMyung-Jae GilMyung-Woo LeeSeung-Wha Yoo
    • G06F1300
    • G06F13/4081
    • A hot-plug controller of PCI (Peripheral Components Interconnects) bus using single chip is disclosed. A PCI hot-plug controller using FPGA and ASIC implements all functions necessary for the PCI hot-plug on a single chip, the PCI hot-plug controller includes: System Interface Unit transmitting data via PCI, USB and I2C bus; Register Unit, which is connected to the System Interface Unit, and receives reset control signal, Present Detection signal, Enable signal, LED control signal and physical ID signal from the outside, and stores the signals; Power Control Unit reading data from the Register Unit and outputting signal to control the system power and slot power; and Bus Isolation Unit reading the control signal from the Register Unit and making the signal-line between PCI bus signal and PCI slot ON/OFF.
    • 公开了使用单芯片的PCI(外围组件互连)总线的热插拔控制器。 使用FPGA和ASIC的PCI热插拔控制器在单个芯片上实现PCI热插拔所需的所有功能,PCI热插拔控制器包括:系统接口单元通过PCI,USB和I2C总线传输数据; 寄存器单元,连接到系统接口单元,并从外部接收复位控制信号,当前检测信号,使能信号,LED控制信号和物理ID信号,并存储信号; 电源控制单元从寄存器单元读取数据并输出信号以控制系统电源和插槽电源; 和总线隔离单元读取寄存器单元的控制信号,并使PCI总线信号和PCI插槽之间的信号线开/关。
    • 38. 发明授权
    • Liquid crystal display and method of fabricating the same
    • 液晶显示器及其制造方法
    • US08085368B2
    • 2011-12-27
    • US12684150
    • 2010-01-08
    • Soon-Dong KimSeung-Gyu TaeSe-Jin ChungJun-Hee MoonMyung-Woo Lee
    • Soon-Dong KimSeung-Gyu TaeSe-Jin ChungJun-Hee MoonMyung-Woo Lee
    • G02F1/133
    • G02F1/1362G02F2001/133388G02F2201/58
    • A liquid crystal display and a simple method to fabricate the same are provided, which can accurately measure luminance of an external light. The liquid crystal display includes a substrate; a thin film transistor array formed on the substrate; and a photoelectric conversion element having a reflection pattern formed on at least one side of the substrate, a photoelectric conversion region provided with a first semiconductor region formed on an upper part of the reflection pattern to receive an external light reflected by the reflection pattern, and a dummy pattern formed on an upper part of the photoelectric conversion region with a width corresponding to the first semiconductor region. The photoelectric conversion region may be configured to adjust the quantity of light incident to the thin film transistor array.
    • 提供液晶显示器和制造它的简单方法,其可以精确地测量外部光的亮度。 液晶显示器包括基板; 形成在所述基板上的薄膜晶体管阵列; 以及光电转换元件,其具有形成在所述基板的至少一侧上的反射图案;光电转换区域,设置有形成在所述反射图案的上部的第一半导体区域,以接收由所述反射图案反射的外部光;以及 形成在光电转换区域的上部的虚拟图案,其宽度对应于第一半导体区域。 光电转换区域可以被配置为调节入射到薄膜晶体管阵列的光量。
    • 40. 发明授权
    • PLL having a multi-level voltage-current converter and a method for locking a clock phase using multi-level voltage-current conversion
    • 具有多电平电压 - 电流转换器的PLL和使用多电平电压 - 电流转换来锁定时钟相位的方法
    • US07068111B2
    • 2006-06-27
    • US10894409
    • 2004-07-19
    • Myung-Woo Lee
    • Myung-Woo Lee
    • H03L7/00
    • H03L7/093H03L7/099H03L7/10
    • A phase locked loop (PLL) circuit having a multi-level voltage-current converter and a clock phase locking method using multi-level voltage-current conversion are described. The phase locked loop (PLL) circuit generates an output clock signal that is phase-locked to a reference clock signal. Further, the PLL circuit includes a phase detecting unit, a charge pump unit, a current-voltage converting unit, and a voltage control oscillator. The phase detecting unit detects a phase difference between the reference clock signal and the output clock signal. The charge pump unit generates a pumping voltage in response to an up signal or down signal output from the phase detector. The current-voltage converting unit receives the pumping voltage, converts the pumping voltage into a predetermined first current, and outputs a tuning voltage in response to predetermined selection signals. The voltage control oscillator generates the output clock signal with a frequency that is proportional to the tuning voltage.
    • 描述了具有多电平电压 - 电流转换器的锁相环(PLL)电路和使用多电平电压 - 电流转换的时钟相位锁定方法。 锁相环(PLL)电路产生与参考时钟信号锁相的输出时钟信号。 此外,PLL电路包括相位检测单元,电荷泵单元,电流 - 电压转换单元和电压控制振荡器。 相位检测单元检测参考时钟信号和输出时钟信号之间的相位差。 电荷泵单元响应于从相位检测器输出的上升信号或下降信号产生泵浦电压。 电流 - 电压转换单元接收泵浦电压,将泵浦电压转换成预定的第一电流,并且响应于预定的选择信号输出调谐电压。 电压控制振荡器以与调谐电压成比例的频率产生输出时钟信号。