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31. 发明申请

US20090177933A1 DECOMPRESSOR/PRPG FOR APPLYING PSEUDO-RANDOM AND DETERMINISTIC TEST PATTERNS 有权
标题翻译：适用于伪随机和确定性测试模式的解码器/ PRPG
公开(公告)号：US20090177933A1
公开(公告)日：2009-07-09
申请号：US12402880
申请日：2009-03-12
申请人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
发明人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318335 , G01R31/31813 , G01R31/318385 , G01R31/318547
摘要： A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns.
摘要翻译：微芯片上的新型解压缩器/ PRPG对芯片上的电路不足测试的确定性测试模式进行伪随机测试模式生成和解压缩。解压缩器/ PRPG有两个操作阶段。在伪随机阶段，解压缩器/ PRPG生成伪随机测试图案，其应用于被测电路中的扫描链。在确定性阶段，将外部测试仪的压缩确定性测试模式应用于解压缩器/ PRPG。在通过解压缩器/ PRPG计时到扫描链中时，模式被解压缩。因此，解压缩器/ PRPG提供比简单PRPG更好的故障覆盖，但是没有完整的完整指定的确定性测试模式的成本。

32. 发明申请

US20070016836A1 Test pattern compression for an integrated circuit test environment 有权
标题翻译：用于集成电路测试环境的测试模式压缩
公开(公告)号：US20070016836A1
公开(公告)日：2007-01-18
申请号：US11523111
申请日：2006-09-18
申请人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
发明人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
IPC分类号： G01R31/28
CPC分类号： G01R31/318335 , G01R31/318371 , G01R31/318547
摘要： A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test. Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit. A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell. The equations are solved to obtain the compressed test pattern.
摘要翻译：一种用于压缩被测电路中扫描链应用的测试图案的方法。该方法包括生成与扫描链内的扫描单元相关联的符号表达式。通过将变量分配给提供给被测电路的外部输入通道上的位来创建符号表达式。使用符号仿真，将变量应用于解压缩器以获取符号表达式。使用确定性模式创建测试立方体，该模式为扫描单元分配值以测试集成电路中的故障。通过将测试立方体中的分配值与与相应扫描单元相关联的符号表达式进行等价来表示一组方程式。求解等式以获得压缩测试图案。

33. 发明授权

US06543020B2 Test pattern compression for an integrated circuit test environment 有权
公开(公告)号：US06543020B2
公开(公告)日：2003-04-01
申请号：US09947160
申请日：2001-09-04
申请人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
发明人： Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Jerzy Tyszer
IPC分类号： G06F1100
CPC分类号： G01R31/318335 , G01R31/318371 , G01R31/318547
摘要： A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test. Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit. A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell. The equations are solved to obtain the compressed test pattern.

34. 发明授权

US06353842B1 Method for synthesizing linear finite state machines 有权
公开(公告)号：US06353842B1
公开(公告)日：2002-03-05
申请号：US09620023
申请日：2000-07-20
申请人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
发明人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
IPC分类号： G06F102
CPC分类号： G06F7/584 , G06F2207/583 , H03K3/84
摘要： Method and apparatus for synthesizing high-performance linear finite state machines (LFSMs) such as linear feedback shift registers (LFSRs) or cellular automata (CA). Given a characteristic polynomial for the circuit, the method obtains an original LFSM circuit such as a type I or type II LFSR. Feedback connections within the original circuit are then determined. Subsequently, a number of transformations that shift the feedback connections can be applied in such a way that properties of the original circuit are preserved in a modified LFSM circuit. In particular, if the original circuit is represented by a primitive characteristic polynomial, the method preserves the maximum-length property of the original circuit in the modified circuit and enables the modified circuit to produce the same m-sequence as the original circuit. Through the various transformations, a modified LFSM circuit can be created that provides higher performance through shorter feedback connection lines, fewer levels of logic, and lower internal fan-out.

35. 发明申请

US20110167309A1 DECOMPRESSOR/PRPG FOR APPLYING PSEUDO-RANDOM AND DETERMINISTIC TEST PATTERNS 审中-公开
标题翻译：适用于伪随机和确定性测试模式的解码器/ PRPG
公开(公告)号：US20110167309A1
公开(公告)日：2011-07-07
申请号：US12983815
申请日：2011-01-03
申请人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
发明人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318335 , G01R31/31813 , G01R31/318385 , G01R31/318547
摘要： A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns.
摘要翻译：微芯片上的新型解压缩器/ PRPG对芯片上的电路不足测试的确定性测试模式进行伪随机测试模式生成和解压缩。解压缩器/ PRPG有两个操作阶段。在伪随机阶段，解压缩器/ PRPG生成伪随机测试图案，其应用于被测电路中的扫描链。在确定性阶段，将外部测试仪的压缩确定性测试模式应用于解压缩器/ PRPG。在通过解压缩器/ PRPG计时到扫描链中时，模式被解压缩。因此，解压缩器/ PRPG提供比简单PRPG更好的故障覆盖，但是没有完整的完整指定的确定性测试模式的成本。

36. 发明申请

US20110138242A1 METHOD AND APPARATUS FOR SELECTIVELY COMPACTING TEST RESPONSES 有权
标题翻译：选择性测试反应的方法和装置
公开(公告)号：US20110138242A1
公开(公告)日：2011-06-09
申请号：US12891498
申请日：2010-09-27
申请人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
发明人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318547
摘要： A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments allow selective masking of a variable number of scan chain outputs.
摘要翻译：一种在确定性测试环境中压缩包含未知值或多个故障效应的测试响应的方法和装置。所提出的选择性压实机采用具有用于选择性地将测试响应传递给压实机的选择电路的线性压实机。在一个实施例中，门控逻辑由控制寄存器，解码器和标志寄存器控制。该电路结合任何常规的并行测试响应压缩方案，允许控制电路选择性地使所需扫描链的串行输出以特定时钟速率馈送到并联压实机。第一个标志寄存器确定是否启用所有或只有一些扫描链输出并通过压实器馈送。第二个标志寄存器确定选择器寄存器选择的扫描链是否启用，所有其他扫描链是禁用的，还是禁用所选扫描链，并启用所有其他扫描链。其他实施例允许对可变数目的扫描链输出的选择性掩蔽。

37. 发明授权

US07925465B2 Low power scan testing techniques and apparatus 有权
标题翻译：低功耗扫描测试技术和设备
公开(公告)号：US07925465B2
公开(公告)日：2011-04-12
申请号：US12069752
申请日：2008-02-12
申请人： Xijiang Lin , Dariusz Czysz , Mark Kassab , Grzegorz Mrugalski , Janusz Rajski , Jerzy Tyszer
发明人： Xijiang Lin , Dariusz Czysz , Mark Kassab , Grzegorz Mrugalski , Janusz Rajski , Jerzy Tyszer
IPC分类号： G06F15/00
CPC分类号： G01R31/318575
摘要： Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) architecture). Among the disclosed embodiments are integrated circuits having programmable test stimuli selectors, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuits. Exemplary test pattern generation methods that can be used to generate test patterns for use with any of the disclosed embodiments are also disclosed.
摘要翻译：以下公开了用于在集成电路测试期间降低功耗的方法，装置和系统的代表性实施例。所公开的技术的实施例可以用于提供低功率测试方案，并且可以与各种压缩硬件架构（例如，嵌入式确定性测试（“EDT”）架构）集成。在所公开的实施例中，具有可编程测试刺激选择器，可编程扫描使能电路，可编程时钟使能电路，可编程移位使能电路和/或可编程复位使能电路的集成电路。还公开了可以用于产生用于与任何所公开的实施例一起使用的测试图案的示例性测试图形生成方法。

38. 发明授权

US07865794B2 Decompressor/PRPG for applying pseudo-random and deterministic test patterns 有权
标题翻译：解压缩器/ PRPG用于应用伪随机和确定性测试模式
公开(公告)号：US07865794B2
公开(公告)日：2011-01-04
申请号：US12402880
申请日：2009-03-12
申请人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
发明人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318335 , G01R31/31813 , G01R31/318385 , G01R31/318547
摘要： A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns.
摘要翻译：微芯片上的新型解压缩器/ PRPG对芯片上的电路不足测试的确定性测试模式进行伪随机测试模式生成和解压缩。解压缩器/ PRPG有两个操作阶段。在伪随机阶段，解压缩器/ PRPG生成伪随机测试图案，其应用于被测电路中的扫描链。在确定性阶段，将外部测试仪的压缩确定性测试模式应用于解压缩器/ PRPG。在通过解压缩器/ PRPG计时到扫描链中时，模式被解压缩。因此，解压缩器/ PRPG提供比简单PRPG更好的故障覆盖，但是没有完整的完整指定的确定性测试模式的成本。

39. 发明申请

US20080195346A1 Low power scan testing techniques and apparatus 有权
标题翻译：低功耗扫描测试技术和设备
公开(公告)号：US20080195346A1
公开(公告)日：2008-08-14
申请号：US12069752
申请日：2008-02-12
申请人： Xijiang Lin , Dariusz Czysz , Mark Kassab , Grzegorz Mrugalski , Janusz Rajski , Jerzy Tyszer
发明人： Xijiang Lin , Dariusz Czysz , Mark Kassab , Grzegorz Mrugalski , Janusz Rajski , Jerzy Tyszer
IPC分类号： G06F19/00 , G01R31/02
CPC分类号： G01R31/318575
摘要： Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) architecture). Among the disclosed embodiments are integrated circuits having programmable test stimuli selectors, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuits. Exemplary test pattern generation methods that can be used to generate test patterns for use with any of the disclosed embodiments are also disclosed.
摘要翻译：以下公开了用于在集成电路测试期间降低功耗的方法，装置和系统的代表性实施例。所公开的技术的实施例可以用于提供低功率测试方案，并且可以与各种压缩硬件架构（例如，嵌入式确定性测试（“EDT”）架构）集成。在所公开的实施例中，具有可编程测试刺激选择器，可编程扫描使能电路，可编程时钟使能电路，可编程移位使能电路和/或可编程复位使能电路的集成电路。还公开了可以用于产生用于与任何所公开的实施例一起使用的测试图案的示例性测试图形生成方法。

40. 发明申请

US20070011530A1 Decompressor/PRPG for applying pseudo-random and deterministic test patterns 有权
标题翻译：解压缩器/ PRPG用于应用伪随机和确定性测试模式
公开(公告)号：US20070011530A1
公开(公告)日：2007-01-11
申请号：US11502655
申请日：2006-08-11
申请人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
发明人： Janusz Rajski , Jerzy Tyszer , Mark Kassab , Nilanjan Mukherjee
IPC分类号： G01R31/28
CPC分类号： G01R31/318335 , G01R31/31813 , G01R31/318385 , G01R31/318547
摘要： A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns.
摘要翻译：微芯片上的新型解压缩器/ PRPG对芯片上的电路不足测试的确定性测试模式进行伪随机测试模式生成和解压缩。解压缩器/ PRPG有两个操作阶段。在伪随机阶段，解压缩器/ PRPG生成伪随机测试图案，其应用于被测电路中的扫描链。在确定性阶段，将外部测试仪的压缩确定性测试模式应用于解压缩器/ PRPG。在通过解压缩器/ PRPG计时到扫描链中时，模式被解压缩。因此，解压缩器/ PRPG提供比简单PRPG更好的故障覆盖，但是没有完整的完整指定的确定性测试模式的成本。

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