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31. 发明授权

US08143130B1 Method of manufacturing depletion MOS device 有权
标题翻译：制造耗尽型MOS器件的方法
公开(公告)号：US08143130B1
公开(公告)日：2012-03-27
申请号：US12910051
申请日：2010-10-22
申请人： Tsung-Yi Huang
发明人： Tsung-Yi Huang
IPC分类号： H01L21/8236
CPC分类号： H01L27/0883 , H01L21/823412 , H01L21/823418 , H01L21/823462
摘要： The present invention discloses a method of manufacturing a depletion metal oxide semiconductor (MOS) device. The method includes: providing a substrate; forming a first conductive type well and an isolation region in the substrate to define a device area; defining a drift region, a source, a drain, and a threshold voltage adjustment region, and implanting second conductive type impurities to form the drift region, the source, the drain, and the threshold voltage adjustment region, respectively; defining a breakdown protection region between the drain and the threshold voltage adjustment region, and implanting first conductive type impurities to form the breakdown protection region; and forming a gate in the device area; wherein a part of the breakdown protection region is below the gate, and the breakdown protection region covers an edge of the threshold voltage adjustment region.
摘要翻译：本发明公开了一种制造耗尽金属氧化物半导体（MOS）器件的方法。该方法包括：提供衬底; 在衬底中形成第一导电类型阱和隔离区以限定器件区域; 限定漂移区域，源极，漏极和阈值电压调整区域，以及分别植入第二导电类型杂质以形成漂移区域，源极，漏极和阈值电压调整区域; 限定漏极和阈值电压调整区域之间的击穿保护区域，以及注入第一导电型杂质以形成击穿保护区域; 以及在所述设备区域中形成栅极; 其中所述击穿保护区域的一部分在所述栅极下方，所述击穿保护区域覆盖所述阈值电压调整区域的边缘。

32. 发明授权

US07960786B2 Breakdown voltages of ultra-high voltage devices by forming tunnels 有权
标题翻译：通过形成隧道的超高压装置的击穿电压
公开(公告)号：US07960786B2
公开(公告)日：2011-06-14
申请号：US12170246
申请日：2008-07-09
申请人： Eric Huang , Tsung-Yi Huang , Fu-Hsin Chen , Chyi-Chyuan Huang , Chung-Yeh Wu
发明人： Eric Huang , Tsung-Yi Huang , Fu-Hsin Chen , Chyi-Chyuan Huang , Chung-Yeh Wu
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L21/266 , H01L29/0634 , H01L29/0692 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring of the first conductivity type occupying a top portion of the HVW, wherein at least one of the pre-HVW, the HVW, and the field ring comprises at least two tunnels; an insulation region over the field ring and a portion of the HVW; a drain region in the HVW and adjacent the insulation region; a gate electrode over a portion the insulation region; and a source region on an opposite side of the gate electrode than the drain region.
摘要翻译：半导体结构包括第一导电类型的半导体衬底; 在所述半导体衬底中的预高压阱（预HVW），其中所述预HVW具有与所述第一导电类型相反的第二导电类型; 在HVW之前的高压井（HVW），其中HVW是第二导电类型; 所述第一导电类型的场环占据所述HVW的顶部部分，其中所述预HVW，所述HVW和所述场环中的至少一个包括至少两个隧道; 在场环上的绝缘区域和HVW的一部分; 在HVW中的漏极区域并且邻近绝缘区域; 绝缘区域的一部分上的栅电极; 以及栅极电极的与漏极区域相反的一侧的源极区域。

33. 发明授权

US07768071B2 Stabilizing breakdown voltages by forming tunnels for ultra-high voltage devices 有权
标题翻译：通过形成超高压设备的隧道来稳定击穿电压
公开(公告)号：US07768071B2
公开(公告)日：2010-08-03
申请号：US12170285
申请日：2008-07-09
申请人： Eric Huang , Tsung-Yi Huang , Fu-Hsin Chen , Chyi-Chyuan Huang , Puo-Yu Chiang
发明人： Eric Huang , Tsung-Yi Huang , Fu-Hsin Chen , Chyi-Chyuan Huang , Puo-Yu Chiang
IPC分类号： H01L23/62
CPC分类号： H01L29/0847 , H01L21/266 , H01L29/0634 , H01L29/0692 , H01L29/42368 , H01L29/66659 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring of the first conductivity type occupying a top portion of the HVW; and a tunnel of the first conductivity type in the pre-HVW and the HVW, and electrically connecting the field ring and the semiconductor substrate.
摘要翻译：半导体结构包括第一导电类型的半导体衬底; 在所述半导体衬底中的预高压阱（预HVW），其中所述预HVW具有与所述第一导电类型相反的第二导电类型; 在HVW之前的高压井（HVW），其中HVW是第二导电类型; 第一导电类型的场环占据HVW的顶部; 以及预HVW和HVW中的第一导电类型的隧道，并且电场连接场环和半导体衬底。

34. 发明授权

US07723785B2 High performance power MOS structure 有权
标题翻译：高性能功率MOS结构
公开(公告)号：US07723785B2
公开(公告)日：2010-05-25
申请号：US11831689
申请日：2007-07-31
申请人： Yu Wen Chen , Fu-Hsin Chen , Tsung-Yi Huang , Yt Tsai
发明人： Yu Wen Chen , Fu-Hsin Chen , Tsung-Yi Huang , Yt Tsai
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L21/26586 , H01L29/086 , H01L29/0878 , H01L29/402 , H01L29/66689 , H01L29/7817
摘要： A semiconductor device includes a source region and a drain region disposed in a substrate wherein the source and drain regions have a first type of dopant; a gate electrode formed on the substrate interposed laterally between the source and drain regions; a gate spacer disposed on the substrate and laterally between the source region and the gate electrode, adjacent a side of the gate electrode; and a conductive feature embedded in the gate spacer.
摘要翻译：半导体器件包括设置在衬底中的源区和漏区，其中源区和漏区具有第一类掺杂剂; 形成在所述基板上的栅极电极，横向插入在所述源极和漏极区域之间; 栅极间隔物，设置在所述基板上，并且在所述源极区域和所述栅极电极之间的横向上与所述栅电极的一侧相邻; 以及嵌入栅极间隔物中的导电特征。

35. 发明申请

US20090032868A1 HIGH PERFORMANCE POWER MOS STRUCTURE 有权
标题翻译：高性能功率MOS结构
公开(公告)号：US20090032868A1
公开(公告)日：2009-02-05
申请号：US11831689
申请日：2007-07-31
申请人： Yu Wen Chen , Fu-Hsin Chen , Tsung-Yi Huang , Yt Tsai
发明人： Yu Wen Chen , Fu-Hsin Chen , Tsung-Yi Huang , Yt Tsai
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L21/26586 , H01L29/086 , H01L29/0878 , H01L29/402 , H01L29/66689 , H01L29/7817
摘要： A semiconductor device includes a source region and a drain region disposed in a substrate wherein the source and drain regions have a first type of dopant; a gate electrode formed on the substrate interposed laterally between the source and drain regions; a gate spacer disposed on the substrate and laterally between the source region and the gate electrode, adjacent a side of the gate electrode; and a conductive feature embedded in the gate spacer.
摘要翻译：半导体器件包括设置在衬底中的源区和漏区，其中源区和漏区具有第一类掺杂剂; 形成在所述基板上的栅极电极，横向插入在所述源极和漏极区域之间; 栅极间隔物，设置在所述基板上，并且在所述源极区域和所述栅极电极之间的横向上与所述栅电极的一侧相邻; 以及嵌入栅极间隔物中的导电特征。

36. 发明申请

US20080211026A1 Coupling well structure for improving HVMOS performance 审中-公开
标题翻译：耦合井结构，以改善HVMOS性能
公开(公告)号：US20080211026A1
公开(公告)日：2008-09-04
申请号：US11594508
申请日：2006-11-08
申请人： Hsueh-Liang Chou , Chen-Bau Wu , Weng-Chu Chu , Tsung-Yi Huang , Fu-Jier Fan
发明人： Hsueh-Liang Chou , Chen-Bau Wu , Weng-Chu Chu , Tsung-Yi Huang , Fu-Jier Fan
IPC分类号： H01L23/62
CPC分类号： H01L29/66477 , H01L21/28 , H01L29/1045 , H01L29/36 , H01L29/66128 , H01L29/66659 , H01L29/7835 , H01L29/8611
摘要： A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.
摘要翻译：半导体结构包括衬底，覆盖衬底的第一导电类型的第一阱区，覆盖衬底的与第一导电类型相反的第二导电类型的第二阱区，与第一阱和第二阱相邻的衬垫区区域，在所述第一阱区域的一部分中并且从所述第一阱区域的顶表面延伸到所述第一阱区域中的绝缘区域;从所述第一阱区域延伸到所述第二阱区域的栅极电介质，其中所述栅极电介质具有绝缘区域上的一部分，以及栅极电介质上的栅电极。

37. 发明申请

US20150123198A1 HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：高压器件及其制造方法
公开(公告)号：US20150123198A1
公开(公告)日：2015-05-07
申请号：US14592306
申请日：2015-01-08
申请人： Tsung-Yi Huang , Chien-Hao Huang
发明人： Tsung-Yi Huang , Chien-Hao Huang
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L21/823418 , H01L29/0634 , H01L29/0692 , H01L29/0886 , H01L29/1045 , H01L29/41758 , H01L29/423 , H01L29/66659 , H01L29/7835
摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a substrate, having an isolation structure for defining a device region; a drift region located in the device region, wherein from top view, the drift region includes multiple sub-regions separated from one another but are electrically connected with one another; a source and a drain in the device region; and a gate on the surface of the substrate and between the source and drain in the device region.
摘要翻译：本发明公开了一种高压器件及其制造方法。高电压装置包括：具有用于限定器件区域的隔离结构的衬底; 位于所述器件区域中的漂移区域，其中，从顶视图，所述漂移区域包括彼此分离但彼此电连接的多个子区域; 设备区域中的源极和漏极; 以及在衬底的表面上以及器件区域中的源极和漏极之间的栅极。

38. 发明授权

US09018070B2 Transient voltage suppressor circuit, and diode device therefor and manufacturing method thereof 有权
标题翻译：瞬态电压抑制电路及其二极管装置及其制造方法
公开(公告)号：US09018070B2
公开(公告)日：2015-04-28
申请号：US14482858
申请日：2014-09-10
申请人： Tsung-Yi Huang , Jin-Lian Su
发明人： Tsung-Yi Huang , Jin-Lian Su
IPC分类号： H01L21/8222 , H01L29/66 , H01L27/08 , H01L27/02 , H01L21/265 , H01L21/762 , H01L29/06
CPC分类号： H01L29/66136 , H01L21/265 , H01L21/76224 , H01L27/0255 , H01L27/0814 , H01L29/0649
摘要： The present invention discloses a transient voltage suppressor (TVS) circuit, and a diode device therefor and a manufacturing method thereof. The TVS circuit is for coupling to a protected circuit to limit amplitude of a transient voltage which is inputted to the protected circuit. The TVS circuit includes a suppressor device and at least a diode device. The diode device is formed in a substrate, which includes: a well formed in the substrate; a separation region formed beneath the upper surface; a anode region and a cathode region, which are formed at two sides of the separation region beneath the upper surface respectively, wherein the anode region and the cathode region are separated by the separation region; and a buried layer, which is formed in the substrate below the well with a higher impurity density and a same conductive type as the well.
摘要翻译：本发明公开了一种瞬态电压抑制器（TVS）电路及其二极管装置及其制造方法。 TVS电路用于耦合到受保护电路以限制输入到保护电路的瞬态电压的幅度。 TVS电路包括抑制器装置和至少二极管装置。二极管器件形成在衬底中，其包括：在衬底中形成的阱; 形成在所述上表面下方的分离区域; 阳极区域和阴极区域，其分别形成在上表面下方的分离区域的两侧，其中阳极区域和阴极区域被分离区域分离; 以及掩埋层，其形成在阱下方的衬底中，具有较高的杂质密度和与该阱相同的导电类型。

39. 发明申请

US20150097269A1 TRANSIENT VOLTAGE SUPPRESSION DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：瞬态电压抑制装置及其制造方法
公开(公告)号：US20150097269A1
公开(公告)日：2015-04-09
申请号：US14049028
申请日：2013-10-08
申请人： Tsung-Yi Huang , Wu-Te Weng
发明人： Tsung-Yi Huang , Wu-Te Weng
IPC分类号： H01L27/02 , H01L29/66 , H01L29/866 , H01L29/73
CPC分类号： H01L27/0259 , H01L29/861 , H01L29/87
摘要： The present invention discloses a transient voltage suppression (TVS) device and a manufacturing method thereof. The TVS device includes: a conductive layer; a P-type semiconductor substrate, which is formed on the conductive layer; an N-type buried layer, which is formed on the semiconductor substrate; a P-type lightly doped layer, which is formed on the buried layer; a P-type cap region, which is formed on the lightly doped layer; and an N-type reverse region, which is formed on the cap region, wherein a Zener diode includes the reverse region and the cap region, and an NPN bipolar junction transistor (BJT) includes the reverse region, the cap region, the lightly doped layer and the buried layer.
摘要翻译：本发明公开了一种瞬态电压抑制（TVS）装置及其制造方法。 TVS装置包括：导电层; 形成在导电层上的P型半导体衬底; 形成在半导体衬底上的N型掩埋层; 形成在埋层上的P型轻掺杂层; 形成在轻掺杂层上的P型帽区; 和N型反向区域，其形成在帽区域上，其中齐纳二极管包括反向区域和帽区域，并且NPN双极结型晶体管（BJT）包括反向区域，帽区域，轻掺杂层和埋层。

40. 发明申请

US20150084060A1 INSULATED GATE BIPOLAR TRANSISTOR AND MANUFACTURING METHOD THEREOF 有权
标题翻译：绝缘栅双极晶体管及其制造方法
公开(公告)号：US20150084060A1
公开(公告)日：2015-03-26
申请号：US14464220
申请日：2014-08-20
申请人： Chih-Fang Huang , Tsung-Yi Huang , Chien-Wei Chiu , Tsung-Yu Yang , Ting-Fu Chang , Tsung-Chieh Hsiao , Ya-Hsien Liu , Po-Chin Peng
发明人： Chih-Fang Huang , Tsung-Yi Huang , Chien-Wei Chiu , Tsung-Yu Yang , Ting-Fu Chang , Tsung-Chieh Hsiao , Ya-Hsien Liu , Po-Chin Peng
IPC分类号： H01L29/73 , H01L29/66 , H01L29/20
CPC分类号： H01L29/66325 , H01L27/0722 , H01L29/1095 , H01L29/2003 , H01L29/201 , H01L29/42316 , H01L29/66462 , H01L29/7787
摘要： The present invention discloses an insulated gate bipolar transistor (IGBT) and a manufacturing method thereof. The IGBT includes: a gallium nitride (GaN) substrate, a first GaN layer with a first conductive type, a second GaN layer with a first conductive type, a third GaN layer with a second conductive type or an intrinsic conductive type, and a gate formed on the GaN substrate. The first GaN layer is formed on the GaN substrate and has a side wall vertical to the GaN substrate. The second GaN layer is formed on the GaN substrate and is separated from the first GaN layer by the gate. The third GaN layer is formed on the first GaN layer and is separated from the GaN substrate by the first GaN layer. The gate has a side plate adjacent to the side wall in a lateral direction to control a channel.
摘要翻译：本发明公开了一种绝缘栅双极晶体管（IGBT）及其制造方法。 IGBT包括：氮化镓（GaN）衬底，具有第一导电类型的第一GaN层，具有第一导电类型的第二GaN层，具有第二导电类型或本征导电类型的第三GaN层，以及栅极形成在GaN衬底上。第一GaN层形成在GaN衬底上并具有垂直于GaN衬底的侧壁。第二GaN层形成在GaN衬底上，并通过栅极与第一GaN层分离。第三GaN层形成在第一GaN层上，并通过第一GaN层与GaN衬底分离。门具有在横向方向上与侧壁相邻的侧板以控制通道。

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