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31. 发明授权

US08495342B2 Configuring plural cores to perform an instruction having a multi-core characteristic 有权
标题翻译：配置多个内核以执行具有多核特性的指令
公开(公告)号：US08495342B2
公开(公告)日：2013-07-23
申请号：US12335921
申请日：2008-12-16
申请人： Louis B. Capps, Jr. , Michael J. Shapiro , Robert H. Bell, Jr. , Thomas E. Cook , William E. Burky
发明人： Louis B. Capps, Jr. , Michael J. Shapiro , Robert H. Bell, Jr. , Thomas E. Cook , William E. Burky
IPC分类号： G06F9/30
CPC分类号： G06F9/5061 , G06F9/3842 , G06F9/3851 , G06F9/3887
摘要： A processor having multiple cores coordinates functions performed on the cores to automatically, dynamically and repeatedly reconfigure the cores for optimal performance based on characteristics of currently executing software. A core running a thread detects a multi-core characteristic of the thread and assigns one or more other cores to the thread to dynamically combine the cores into what functionally amounts to a common core for more efficient execution of the thread.
摘要翻译：具有多个核的处理器协调在核上执行的功能，以基于当前执行的软件的特性自动，动态地和重复地重新配置核以获得最佳性能。运行线程的核心检测线程的多核特性，并为线程分配一个或多个其他内核，以将内核动态组合到功能上相当于共同核心的内核，从而更有效地执行线程。

32. 发明授权

US07904870B2 Method and apparatus for integrated circuit design model performance evaluation using basic block vector clustering and fly-by vector clustering 有权
标题翻译：集成电路设计模型性能评估的方法和装置，采用基本的块矢量聚类和飞行矢量聚类
公开(公告)号：US07904870B2
公开(公告)日：2011-03-08
申请号：US12112035
申请日：2008-04-30
申请人： Robert H. Bell, Jr. , Wen-Tzer Thomas Chen , Venkat Rajeev Indukuru , Pattabi Michael Seshadri , Madhavi Gopal Valluri
发明人： Robert H. Bell, Jr. , Wen-Tzer Thomas Chen , Venkat Rajeev Indukuru , Pattabi Michael Seshadri , Madhavi Gopal Valluri
IPC分类号： G06F9/455
CPC分类号： G06F17/5022 , G01R31/318357 , G06F11/3428 , G06F11/3457 , G06F11/3664
摘要： A test system or simulator includes an enhanced IC test application sampling software program that executes test application software on a semiconductor die IC design model. The enhanced test application sampling software may include trace, simulation point, CPI error, clustering, instruction budgeting, and other programs. The enhanced test application sampling software generates basic block vectors (BBVs) and fly-by vectors (FBVs) from instruction trace analysis of test application software workloads. The enhanced test application sampling software utilizes the microarchitecture dependent information to generate the FBVs to select representative instruction intervals from the test application software. The enhanced test application sampling software generates a reduced representative test application software program from the BBV and FBV data utilizing a global instruction budgeting analysis method. Designers use the test system with enhanced test application sampling software to evaluate IC design models by using the representative test application software program.
摘要翻译：测试系统或模拟器包括在半导体芯片IC设计模型上执行测试应用软件的增强型IC测试应用采样软件程序。增强的测试应用程序采样软件可能包括跟踪，模拟点，CPI错误，聚类，指令预算和其他程序。增强的测试应用采样软件从测试应用软件工作负载的指令跟踪分析中生成基本块向量（BBV）和飞越向量（FBV）。增强的测试应用采样软件利用微架构依赖信息生成FBV，以从测试应用软件中选择代表性指令间隔。增强的测试应用采样软件利用全球指令预算分析方法，从BBV和FBV数据生成代表性测试应用软件程序。设计人员使用带有增强型测试应用程序采样软件的测试系统，通过使用代表性的测试应用软件程序来评估IC设计模型。

33. 发明授权

US07568076B2 Variable store gather window 有权
标题翻译：变量存储收集窗口
公开(公告)号：US07568076B2
公开(公告)日：2009-07-28
申请号：US11836872
申请日：2007-08-10
申请人： Robert H. Bell, Jr. , Hugh Shen , Jeffrey Adam Stuecheli , Derek Edward Williams
发明人： Robert H. Bell, Jr. , Hugh Shen , Jeffrey Adam Stuecheli , Derek Edward Williams
IPC分类号： G06F12/08
CPC分类号： G06F9/3824 , G06F9/30043 , G06F12/0897
摘要： A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to lower level memory. In addition, the store queue includes dispatch logic that varies a size of the store gathering window to optimize store performance for different store behaviors and workloads.
摘要翻译：处理器包括执行存储指令以获得存储操作的至少一个指令执行单元和耦合到指令执行单元的存储队列。存储队列包括队列条目，其中存储队列在存储收集窗口期间收集多个存储操作，以获得指向低级存储器的写入事务的数据部分。此外，商店队列包括调度逻辑，其改变商店收集窗口的大小以优化针对不同商店行为和工作负载的存储性能。

34. 发明授权

US07543120B2 Processor and data processing system employing a variable store gather window 有权
标题翻译：处理器和数据处理系统采用可变存储收集窗口
公开(公告)号：US07543120B2
公开(公告)日：2009-06-02
申请号：US11952596
申请日：2007-12-07
申请人： Robert H. Bell, Jr. , Hugh Shen , Jeffrey Adam Stuecheli , Derek Edward Williams
发明人： Robert H. Bell, Jr. , Hugh Shen , Jeffrey Adam Stuecheli , Derek Edward Williams
IPC分类号： G06F12/08
CPC分类号： G06F9/3824 , G06F9/30043 , G06F12/0897
摘要： A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to lower level memory. In addition, the store queue includes dispatch logic that varies a size of the store gathering window to optimize store performance for different store behaviors and workloads.
摘要翻译：处理器包括执行存储指令以获得存储操作的至少一个指令执行单元和耦合到指令执行单元的存储队列。存储队列包括队列条目，其中存储队列在存储收集窗口期间收集多个存储操作，以获得指向低级存储器的写入事务的数据部分。此外，商店队列包括调度逻辑，其改变商店收集窗口的大小以优化针对不同商店行为和工作负载的存储性能。

35. 发明授权

US07366851B2 Processor, method, and data processing system employing a variable store gather window 有权
标题翻译：处理器，方法和数据处理系统采用变量存储收集窗口
公开(公告)号：US07366851B2
公开(公告)日：2008-04-29
申请号：US10922272
申请日：2004-08-19
申请人： Robert H. Bell, Jr. , Hugh Shen , Jeffrey Adam Stuecheli , Derek Edward Williams
发明人： Robert H. Bell, Jr. , Hugh Shen , Jeffrey Adam Stuecheli , Derek Edward Williams
IPC分类号： G06F12/08
CPC分类号： G06F9/3824 , G06F9/30043 , G06F12/0897
摘要： A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to lower level memory. In addition, the store queue includes dispatch logic that varies a size of the store gathering window to optimize store performance for different store behaviors and workloads.
摘要翻译：处理器包括执行存储指令以获得存储操作的至少一个指令执行单元和耦合到指令执行单元的存储队列。存储队列包括队列条目，其中存储队列在存储收集窗口期间收集多个存储操作，以获得指向低级存储器的写入事务的数据部分。此外，商店队列包括调度逻辑，其改变商店收集窗口的大小以优化针对不同商店行为和工作负载的存储性能。

36. 发明授权

US10169087B2 Technique for preserving memory affinity in a non-uniform memory access data processing system 有权
公开(公告)号：US10169087B2
公开(公告)日：2019-01-01
申请号：US13015733
申请日：2011-01-28
申请人： Mathew Accapadi , Robert H. Bell, Jr. , Men-Chow Chiang , Hong L. Hua
发明人： Mathew Accapadi , Robert H. Bell, Jr. , Men-Chow Chiang , Hong L. Hua
IPC分类号： G06F15/16 , G06F9/50
摘要： Techniques for preserving memory affinity in a computer system is disclosed. In response to a request for memory access to a page within a memory affinity domain, a determination is made if the request is initiated by a processor associated with the memory affinity domain. If the request is not initiated by a processor associated with the memory affinity domain, a determination is made if there is a page ID match with an entry within a page migration tracking module associated with the memory affinity domain. If there is no page ID match, an entry is selected within the page migration tracking module to be updated with a new page ID and a new memory affinity ID. If there is a page ID match, then another determination is made whether or not there is a memory affinity ID match with the entry with the page ID field match. If there is no memory affinity ID match, the entry is updated with a new memory affinity ID; and if there is a memory affinity ID match, an access counter of the entry is incremented.

37. 发明授权

US09135142B2 Workload performance projection for future information handling systems using microarchitecture dependent data 有权
标题翻译：使用微架构依赖数据的未来信息处理系统的工作负载性能预测
公开(公告)号：US09135142B2
公开(公告)日：2015-09-15
申请号：US12343482
申请日：2008-12-24
申请人： Robert H. Bell, Jr. , Luigi Brochard , Donald Robert DeSota , Venkat R. Indukuru , Rajendra D. Panda , Sameh S. Sharkawi
发明人： Robert H. Bell, Jr. , Luigi Brochard , Donald Robert DeSota , Venkat R. Indukuru , Rajendra D. Panda , Sameh S. Sharkawi
IPC分类号： G06F3/01 , G01C7/00 , G01C7/04 , G06F3/00 , G06F11/36 , G06F11/34
CPC分类号： G06F11/3612 , G06F11/3428 , G06F11/3457 , G06F11/3466 , G06F2201/88
摘要： A performance projection system includes a test IHS and a currently existing IHS. The performance projection system includes surrogate programs and user application software. The test IHS employs a memory that includes a virtual future IHS, currently existing IHS, surrogate programs, and user application software for determination of runtime and HW counter performance data. The user application software and surrogate programs execute on the currently existing MS to provide designers with runtime data and HW counter or microarchitecture dependent data. Designers execute surrogate programs on the future IHS to provide runtime and HW counter data. Designers normalize and weight the runtime and HW counter data to provide a representative surrogate program for comparison to user application software performance on the future IHS. Using a scaling factor, designers may generate a projection of runtime performance for the user application software executing on the future IHS.
摘要翻译：性能投影系统包括测试IHS和当前存在的IHS。性能投影系统包括代理程序和用户应用软件。测试IHS采用包含虚拟未来IHS，现有IHS，替代程序和用户应用软件的存储器，用于确定运行时和硬件计数器性能数据。用户应用软件和代理程序在当前现有的MS上执行，为设计人员提供运行时数据和HW计数器或微体系结构依赖数据。设计人员在未来的IHS上执行代理程序来提供运行时和硬件计数器数据。设计师对运行时和HW计数器数据进行规范化和加权，以提供代表性的代理程序，以便与未来IHS的用户应用软件性能进行比较。使用缩放因子，设计人员可以为未来IHS上执行的用户应用软件生成运行时性能的投影。

38. 发明授权

US08806153B2 Partial line cache write injector for direct memory access write 有权
标题翻译：部分行缓存写入注入器用于直接内存访问写入
公开(公告)号：US08806153B2
公开(公告)日：2014-08-12
申请号：US13031809
申请日：2011-02-22
申请人： Robert H. Bell, Jr. , Herman Dietrich Dierks , Hong Lam Hua , Mysore Sathyanarayana Srinivas
发明人： Robert H. Bell, Jr. , Herman Dietrich Dierks , Hong Lam Hua , Mysore Sathyanarayana Srinivas
IPC分类号： G06F12/04 , G06F11/10 , G06F12/12
CPC分类号： G06F12/04 , G06F11/1056 , G06F12/0806 , G06F12/0888 , G06F12/12 , G06F2212/621
摘要： A cache within a computer system receives a partial write request and identifies a cache hit of a cache line. The cache line corresponds to the partial write request and includes existing data. In turn, the cache receives partial write data and merges the partial write data with the existing data into the cache line. In one embodiment, the existing data is “modified” or “dirty.” In another embodiment, the existing data is “shared.” In this embodiment, the cache changes the state of the cache line to indicate the storing of the partial write data into the cache line.
摘要翻译：计算机系统内的高速缓存接收部分写请求并识别高速缓存行的高速缓存命中。高速缓存线对应于部分写入请求并且包括现有数据。反过来，高速缓存接收部分写入数据，并将部分写入数据与现有数据合并到高速缓存行中。在一个实施例中，现有数据被“修改”或“脏”。在另一个实施例中，现有数据是“共享”。在该实施例中，高速缓存改变高速缓存线的状态以指示部分写数据的存储进入缓存行。

39. 发明授权

US08751751B2 Method and apparatus for minimizing cache conflict misses 有权
标题翻译：用于最小化缓存冲突漏洞的方法和装置
公开(公告)号：US08751751B2
公开(公告)日：2014-06-10
申请号：US13015771
申请日：2011-01-28
申请人： Robert H. Bell, Jr. , Men-Chow Chiang , Hong L. Hua
发明人： Robert H. Bell, Jr. , Men-Chow Chiang , Hong L. Hua
IPC分类号： G06F12/00 , G06F12/08 , G06F12/10
CPC分类号： G06F12/0864 , G06F12/1018 , G06F12/1036
摘要： A method for minimizing cache conflict misses is disclosed. A translation table capable of facilitating the translation of a virtual address to a real address during a cache access is provided. The translation table includes multiple entries, and each entry of the translation table includes a page number field and a hash value field. A hash value is generated from a first group of bits within a virtual address, and the hash value is stored in the hash value field of an entry within the translation table. In response to a match on the entry within the translation table during a cache access, the hash value of the matched entry is retrieved from the translation table, and the hash value is concatenated with a second group of bits within the virtual address to form a set of indexing bits to index into a cache set.
摘要翻译：公开了一种最小化缓存冲突漏洞的方法。提供了一种能够有助于在高速缓存访问期间将虚拟地址转换为真实地址的转换表。翻译表包括多个条目，并且翻译表的每个条目包括页码字段和散列值字段。从虚拟地址内的第一组比特生成哈希值，并将哈希值存储在转换表内的条目的哈希值字段中。响应于高速缓存访问期间在转换表内的条目的匹配，从转换表中检索匹配条目的散列值，并且将散列值与虚拟地址中的第二组位相连，以形成一组索引位索引到高速缓存集中。

40. 发明授权

US08745362B2 Operating system aware branch predictor using a dynamically reconfigurable branch history table 有权
标题翻译：使用动态可重配置分支历史表的操作系统感知分支预测器
公开(公告)号：US08745362B2
公开(公告)日：2014-06-03
申请号：US12823288
申请日：2010-06-25
申请人： Robert H. Bell, Jr. , Wen-Tzer Thomas Chen
发明人： Robert H. Bell, Jr. , Wen-Tzer Thomas Chen
IPC分类号： G06F9/00
CPC分类号： G06F9/5011 , G06F9/3848 , G06F2209/507
摘要： A processor resource manager assigns a branch history resource to a first execution mode. The branch history resource is utilized for predicting a branch direction of a branch instruction. Next, the resource manager logs a number of branch mispredictions that occur while the processor executes a second execution mode. The resource manager, in turn, reassigns the branch history resource to the second execution mode based upon the number of branch mispredictions.
摘要翻译：处理器资源管理器将分支历史资源分配给第一执行模式。分支历史资源用于预测分支指令的分支方向。接下来，资源管理器记录在处理器执行第二执行模式时发生的多个分支错误预测。资源管理器又根据分支错误预测的数量将分支历史资源重新分配到第二执行模式。

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