专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US07053654B1 PLD lookup table including transistors of more than one oxide thickness 有权
标题翻译： PLD查找表包括多于一个氧化物厚度的晶体管
公开(公告)号：US07053654B1
公开(公告)日：2006-05-30
申请号：US10869139
申请日：2004-06-15
申请人： Steven P. Young , Venu M. Kondapalli , Martin L. Voogel
发明人： Steven P. Young , Venu M. Kondapalli , Martin L. Voogel
IPC分类号： G06F7/38
CPC分类号： H03K19/1778 , H03K19/1737 , H03K19/17728
摘要： A structure that can be used, for example, to implement a lookup table for a programmable logic device (PLD). The structure includes configuration memory cells, pass transistors, and a buffer. The pass transistors pass the output of a selected configuration memory cell to the buffer, and are controlled by data input signals of the structure. The pass transistors have a first oxide thickness and are controlled by a value having a first operating voltage. The memory cells and buffer include transistors having a second oxide thickness thinner than the first oxide thickness, and operate at a second operating voltage lower than the first operating voltage. The data input signals are provided at the first operating voltage. Some embodiments include data generating circuits that include transistors having the first oxide thickness. Gate lengths can also vary between the memory cell transistors, pass transistors, buffer transistors, and data generating circuits.
摘要翻译：可用于例如实现可编程逻辑器件（PLD）的查找表的结构。该结构包括配置存储单元，传输晶体管和缓冲器。传输晶体管将所选配置存储单元的输出传递到缓冲器，并由结构的数据输入信号控制。传输晶体管具有第一氧化物厚度并且由具有第一工作电压的值控制。存储单元和缓冲器包括具有比第一氧化物厚度薄的第二氧化物厚度的晶体管，并且在低于第一工作电压的第二工作电压下工作。在第一工作电压下提供数据输入信号。一些实施例包括包括具有第一氧化物厚度的晶体管的数据产生电路。栅极长度也可以在存储单元晶体管，传输晶体管，缓冲晶体管和数据产生电路之间变化。

32. 发明授权

US06768335B1 Integrated circuit multiplexer including transistors of more than one oxide thickness 有权
标题翻译：集成电路多路复用器包括多于一个氧化物厚度的晶体管
公开(公告)号：US06768335B1
公开(公告)日：2004-07-27
申请号：US10354520
申请日：2003-01-30
申请人： Steven P. Young , Michael J. Hart , Venu M. Kondapalli , Martin L. Voogel
发明人： Steven P. Young , Michael J. Hart , Venu M. Kondapalli , Martin L. Voogel
IPC分类号： G06F738
CPC分类号： H03K17/005 , H03K17/693 , H03K19/17736 , H03K19/1778
摘要： A multiplexer that can be used, for example, in a programmable logic device (PLD). The multiplexer includes a plurality of pass transistors passing a selected one of several input values to an internal node, which drives a buffer that provides the multiplexer output signal. The pass transistors can be controlled, for example, by values stored in memory cells of a PLD. The pass transistors have a first oxide thickness and are controlled by a value having a first operating voltage. The buffer includes transistors having a second and thinner oxide thickness, and is operated at a second and lower operating voltage. Where memory cells are used to control the pass transistors, the memory cells include transistors having the first oxide thickness and operate at the first operating voltage. Some embodiments also include transistors of varying gate length for each of the pass transistors, buffer transistors, and memory cell transistors.
摘要翻译：可以用于例如可编程逻辑器件（PLD）中的多路复用器。多路复用器包括将多个输入值中选择的一个输入值传送到内部节点的多个传输晶体管，驱动提供多路复用器输出信号的缓冲器。可以例如通过存储在PLD的存储器单元中的值来控制传输晶体管。传输晶体管具有第一氧化物厚度并且由具有第一工作电压的值控制。缓冲器包括具有第二和较薄氧化物厚度的晶体管，并且在第二和较低工作电压下操作。在使用存储器单元来控制传输晶体管的情况下，存储单元包括具有第一氧化物厚度并在第一工作电压下工作的晶体管。一些实施例还包括用于每个传输晶体管，缓冲晶体管和存储单元晶体管的栅极长度变化的晶体管。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式