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31. 发明授权

US08181168B1 Memory access assignment for parallel processing architectures 有权
标题翻译：并行处理架构的内存访问分配
公开(公告)号：US08181168B1
公开(公告)日：2012-05-15
申请号：US12028007
申请日：2008-02-07
申请人： Walter Lee , Robert A. Gottlieb , Vineet Soni , Anant Agarwal , Richard Schooler
发明人： Walter Lee , Robert A. Gottlieb , Vineet Soni , Anant Agarwal , Richard Schooler
IPC分类号： G06F9/445
CPC分类号： G06F8/41 , G06F8/445 , G06F12/0837
摘要： A system comprises a plurality of computation units interconnected by an interconnection network. A method for configuring the system comprises forming subsets of instructions corresponding to different portions of a program, the subsets of instructions being related according to a control flow graph; forming one or more memory analysis regions that include one or more of the subsets of instructions, where each subset of instructions is included in a single memory analysis region; analyzing each memory analysis region to partition memory objects and instructions that access the memory objects into equivalence classes such that instructions within an equivalence class only access objects in the same equivalence class; and assigning memory access instructions a given equivalence class to one of the computation units for execution on the assigned computation unit.
摘要翻译：一种系统包括由互连网互连的多个计算单元。一种用于配置系统的方法包括形成与节目的不同部分相对应的指令子集，所述指令子集根据控制流程图相关; 形成包括指令子集中的一个或多个的一个或多个存储器分析区域，其中每个指令子集包括在单个存储器分析区域中; 分析每个存储器分析区域以将存储器对象和将存储器对象访问为等价类的指令分区，使得等价类中的指令仅访问相同等价类中的对象; 以及将存储器访问指令分配给给定的等价类别到所述计算单元之一，以便在所分配的计算单元上执行。

32. 发明申请

US20120068263A1 Power Switching Semiconductor Devices Including Rectifying Junction-Shunts 有权
标题翻译：功率开关半导体器件包括整流结分路
公开(公告)号：US20120068263A1
公开(公告)日：2012-03-22
申请号：US13267966
申请日：2011-10-07
申请人： Allen Hefner , Sei-Hyung Ryu , Anant Agarwal
发明人： Allen Hefner , Sei-Hyung Ryu , Anant Agarwal
IPC分类号： H01L29/78
CPC分类号： H01L29/7803 , H01L21/0465 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/41766 , H01L29/6606 , H01L29/66068 , H01L29/7802 , H01L29/7828 , H01L29/861
摘要： A semiconductor device includes a drift layer and a body region that forms a p-n junction with the drift layer. A contactor region is in the body region, and a shunt channel region extends through the body region from the contactor region to the drift layer. The shunt channel region has a length, thickness and doping concentration selected such that: 1) the shunt channel region is fully depleted when zero voltage is applied across the first and second terminals, 2) the shunt channel becomes conductive at a voltages less than the built-in potential of the drift layer to body region p-n junction, and/or 3) the shunt channel is not conductive for voltages that reverse bias the p-n junction between the drift region and the body region.
摘要翻译：半导体器件包括漂移层和与漂移层形成p-n结的体区。接触器区域在体区域中，并且分流通道区域从接触器区域延伸穿过体区域到漂移层。分流沟道区域具有选择的长度，厚度和掺杂浓度，使得：1）当跨越第一和第二端子施加零电压时，并联沟道区域完全耗尽，2）并联沟道在小于内部电位漂移层到体区pn结，和/或3）并联通道对于反向偏置漂移区域和体区之间的pn结的电压是不导通的。

33. 发明授权

US08127111B1 Managing data provided to switches in a parallel processing environment 有权
标题翻译：在并行处理环境中管理提供给交换机的数据
公开(公告)号：US08127111B1
公开(公告)日：2012-02-28
申请号：US12110956
申请日：2008-04-28
申请人： David Wentzlaff , Anant Agarwal
发明人： David Wentzlaff , Anant Agarwal
IPC分类号： G06F15/00
CPC分类号： G06F15/16
摘要： An integrated circuit comprises a plurality of tiles. Each tile comprises a processor including a storage module, wherein the processor is configured to process multiple streams of instructions, a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles, and coupling circuitry configured to couple data resulting from processing an instruction from at least one of the streams of instructions to the storage module and to the switch.
摘要翻译：集成电路包括多个瓦片。每个瓦片包括包括存储模块的处理器，其中所述处理器被配置为处理多个指令流，开关包括切换电路，以将从其他瓦片到数据路径接收的数据转发到处理器，以及转发其他瓦片从处理器接收的数据到其他瓦片的切换器，以及耦合电路，其被配置为将从指令流中的至少一个处理指令得到的数据耦合到存储模块和交换机。

34. 发明授权

US08112581B1 Caching in multicore and multiprocessor architectures 有权
标题翻译：在多核和多处理器架构中进行缓存
公开(公告)号：US08112581B1
公开(公告)日：2012-02-07
申请号：US12958920
申请日：2010-12-02
申请人： Anant Agarwal , Ian R. Bratt , Matthew Mattina
发明人： Anant Agarwal , Ian R. Bratt , Matthew Mattina
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/0811 , G06F12/0815 , G06F12/0817
摘要： A multicore processor comprises a plurality of cache memories; a plurality of processor cores, each associated with one of the cache memories; one or more memory interfaces providing memory access paths from the cache memories to a main memory; and one or more directory controllers for respective portions of the main memory, each associated with corresponding storage for directory state. Each corresponding storage provides space for maintaining directory state for each memory line that is indicated as stored in at least one of the cache memories such that the space for maintaining directory state is independent of the size of the main memory.
摘要翻译：多核处理器包括多个高速缓冲存储器; 多个处理器核心，每个处理器核心与高速缓冲存储器之一相关联; 一个或多个存储器接口，提供从高速缓冲存储器到主存储器的存储器访问路径; 以及用于主存储器的相应部分的一个或多个目录控制器，每个与用于目录状态的相应存储器相关联。每个对应的存储器提供用于维护指示为存储在至少一个高速缓存存储器中的每个存储器线的目录状态的空间，使得用于维护目录状态的空间与主存储器的大小无关。

35. 发明授权

US07987321B1 Caching in multicore and multiprocessor architectures 有权
标题翻译：在多核和多处理器架构中进行缓存
公开(公告)号：US07987321B1
公开(公告)日：2011-07-26
申请号：US12966686
申请日：2010-12-13
申请人： Anant Agarwal , Ian R. Bratt , Matthew Mattina
发明人： Anant Agarwal , Ian R. Bratt , Matthew Mattina
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/0811 , G06F12/0815 , G06F12/0817
摘要： A multicore processor comprises a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is configured to maintain at least a portion of the cache memory in which each cache line is dynamically managed as either local to the associated processor core or shared among multiple processor cores.
摘要翻译：多核处理器包括多个高速缓存存储器和多个处理器核心，每个处理器核心与高速缓冲存储器之一相关联。至少一些高速缓存存储器中的每一个被配置为保持高速缓冲存储器的至少一部分，其中每个高速缓存行被动态地管理为相关联的处理器核心的本地或在多个处理器核心之间共享。

36. 发明授权

US07853754B1 Caching in multicore and multiprocessor architectures 有权
标题翻译：在多核和多处理器架构中进行缓存
公开(公告)号：US07853754B1
公开(公告)日：2010-12-14
申请号：US11754062
申请日：2007-05-25
申请人： Anant Agarwal , Ian R. Bratt , Matthew Mattina
发明人： Anant Agarwal , Ian R. Bratt , Matthew Mattina
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/0811 , G06F12/0815 , G06F12/0817
摘要： A multicore processor comprises a plurality of cache memories; a plurality of processor cores, each associated with one of the cache memories; one or more memory interfaces providing memory access paths from the cache memories to a main memory; and one or more directory controllers for respective portions of the main memory, each associated with corresponding storage for directory state. Each corresponding storage provides space for maintaining directory state for each memory line that is indicated as stored in at least one of the cache memories such that the space for maintaining directory state is independent of the size of the main memory.
摘要翻译：多核处理器包括多个高速缓冲存储器; 多个处理器核心，每个处理器核心与高速缓冲存储器之一相关联; 一个或多个存储器接口，提供从高速缓冲存储器到主存储器的存储器访问路径; 以及用于主存储器的相应部分的一个或多个目录控制器，每个与用于目录状态的相应存储器相关联。每个对应的存储器提供用于维护指示为存储在至少一个高速缓存存储器中的每个存储器线的目录状态的空间，使得用于维护目录状态的空间与主存储器的大小无关。

37. 发明申请

US20080121993A1 POWER SWITCHING SEMICONDUCTOR DEVICES INCLUDING RECTIFYING JUNCTION-SHUNTS 有权
标题翻译：电源开关半导体器件，包括整流器
公开(公告)号：US20080121993A1
公开(公告)日：2008-05-29
申请号：US11556448
申请日：2006-11-03
申请人： Allen Hefner , Sei-Hyung Ryu , Anant Agarwal
发明人： Allen Hefner , Sei-Hyung Ryu , Anant Agarwal
IPC分类号： H01L29/78 , H01L21/336 , H01L29/861
CPC分类号： H01L29/7803 , H01L21/0465 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/41766 , H01L29/6606 , H01L29/66068 , H01L29/7802 , H01L29/7828 , H01L29/861
摘要： A semiconductor device includes a drift layer having a first conductivity type and a body region adjacent the drift layer. The body region has a second conductivity type opposite the first conductivity type and forms a p-n junction with the drift layer. The device further includes a contactor region in the body region and having the first conductivity type, and a shunt channel region extending through the body region from the contactor region to the drift layer. The shunt channel region has the first conductivity type. The device further includes a first terminal in electrical contact with the body region and the contactor region, and a second terminal in electrical contact with the drift layer. The shunt channel region has a length, thickness and doping concentration selected such that: 1) the shunt channel region is fully depleted when zero voltage is applied across the first and second terminals, 2) the shunt channel becomes conductive at a voltages less than the built-in potential of the drift layer to body region p-n junction, and/or 3) the shunt channel is not conductive for voltages that reverse biase the p-n junction between the drift region and the body region.
摘要翻译：半导体器件包括具有第一导电类型的漂移层和与漂移层相邻的体区。身体区域具有与第一导电类型相反的第二导电类型，并与漂移层形成p-n结。该器件还包括在体区中具有第一导电类型的接触器区域和从接触器区域延伸穿过体区的分流通道区域到漂移层。分流通道区域具有第一导电类型。该装置还包括与主体区域和接触器区域电接触的第一端子和与漂移层电接触的第二端子。分流沟道区域具有选择的长度，厚度和掺杂浓度，使得：1）当跨越第一和第二端子施加零电压时，并联沟道区域完全耗尽，2）并联沟道在小于内部电位漂移层到体区pn结，和/或3）并联通道对于反向偏置漂移区和体区之间的pn结的电压不导通。

38. 发明申请

US20070235757A1 Silicon carbide bipolar junction transistors having epitaxial base regions and multilayer emitters and methods of fabricating the same 有权
标题翻译：具有外延基极区域和多层发射极的碳化硅双极结型晶体管及其制造方法
公开(公告)号：US20070235757A1
公开(公告)日：2007-10-11
申请号：US11229474
申请日：2005-09-16
申请人： Anant Agarwal , Sumithra Krishnaswami , Sei-Hyung Ryu , Edward Hurt
发明人： Anant Agarwal , Sumithra Krishnaswami , Sei-Hyung Ryu , Edward Hurt
IPC分类号： H01L31/00
CPC分类号： H01L29/66068 , H01L29/0804 , H01L29/1004 , H01L29/1608 , H01L29/732
摘要： Bipolar junction transistors (BJTs) are provided including silicon carbide (SiC) substrates. An epitaxial SiC base region is provided on the SiC substrate. The epitaxial SiC base region has a first conductivity type. An epitaxial SiC emitter region is also provided on the SiC substrate. The epitaxial SiC emitter region has a second conductivity type, different from the first conductivity type. The epitaxial SiC emitter region has first and second portions. The first portion is provided on the SiC substrate and the second portion is provided on the first portion. The second portion has a higher carrier concentration than the first portion. Related methods of fabricating BJTs are also provided herein.
摘要翻译：提供双极结晶体管（BJT），包括碳化硅（SiC）衬底。在SiC衬底上设置外延SiC基区。外延SiC基区具有第一导电类型。外延SiC发射极区也设置在SiC衬底上。外延SiC发射极区域具有不同于第一导电类型的第二导电类型。外延SiC发射极区域具有第一和第二部分。第一部分设置在SiC衬底上，第二部分设置在第一部分上。第二部分具有比第一部分更高的载流子浓度。本文还提供了制造BJT的相关方法。

39. 发明授权

US06956238B2 SILICON CARBIDE POWER METAL-OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS HAVING A SHORTING CHANNEL AND METHODS OF FABRICATING SILICON CARBIDE METAL-OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS HAVING A SHORTING CHANNEL 有权
标题翻译：具有短路通道的碳化硅金属氧化物半导体场效应晶体管和制备具有短路通道的碳化硅金属氧化物半导体场效应晶体管的方法
公开(公告)号：US06956238B2
公开(公告)日：2005-10-18
申请号：US09911995
申请日：2001-07-24
申请人： Sei-Hyung Ryu , Anant Agarwal , Mrinal Kanti Das , Lori A. Lipkin , John W. Palmour , Ranbir Singh
发明人： Sei-Hyung Ryu , Anant Agarwal , Mrinal Kanti Das , Lori A. Lipkin , John W. Palmour , Ranbir Singh
IPC分类号： H01L21/04 , H01L21/336 , H01L29/10 , H01L29/12 , H01L29/24 , H01L29/78 , H01L29/161
CPC分类号： H01L29/7802 , H01L21/049 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/7828 , H01L29/7838
摘要： Silicon carbide metal-oxide semiconductor field effect transistors (MOSFETs) and methods of fabricating silicon carbide MOSFETs are provided. The silicon carbide MOSFETs have an n-type silicon carbide drift layer, spaced apart p-type silicon carbide regions in the n-type silicon carbide drift layer and having n-type silicon carbide regions therein, and a nitrided oxide layer. The MOSFETs also have n-type shorting channels extending from respective ones of the n-type silicon carbide regions through the p-type silicon carbide regions to the n-type silicon carbide drift layer. In further embodiments, silicon carbide MOSFETs and methods of fabricating silicon carbide MOSFETs are provided that include a region that is configured to self-deplete the source region, between the n-type silicon carbide regions and the drift layer, adjacent the oxide layer, upon application of a zero gate bias.
摘要翻译：提供了碳化硅金属氧化物半导体场效应晶体管（MOSFET）和制造碳化硅MOSFET的方法。碳化硅MOSFET具有n型碳化硅漂移层，n型碳化硅漂移层中间隔开的p型碳化硅区域，其中具有n型碳化硅区域和氮化氧化物层。 MOSFET还具有从n型碳化硅区域中的相应的n型碳化硅区域延伸穿过p型碳化硅区域到n型碳化硅漂移层的n型短路通道。在另外的实施例中，提供了碳化硅MOSFET和制造碳化硅MOSFET的方法，其包括被配置为在n型碳化硅区域和与氧化物层相邻的漂移层之间自耗光源区域的区域零门偏置的应用。

40. 发明授权

US06514779B1 Large area silicon carbide devices and manufacturing methods therefor 有权
标题翻译：大面积碳化硅器件及其制造方法
公开(公告)号：US06514779B1
公开(公告)日：2003-02-04
申请号：US09981523
申请日：2001-10-17
申请人： Sei-Hyung Ryu , Anant Agarwal , Craig Capell , John W. Palmour
发明人： Sei-Hyung Ryu , Anant Agarwal , Craig Capell , John W. Palmour
IPC分类号： G01R3126
CPC分类号： G01R31/2831 , H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： A silicon carbide device is fabricated by forming a plurality of a same type of silicon carbide devices on at least a portion of a silicon carbide wafer in a predefined pattern. The silicon carbide devices have corresponding first contacts on a first face of the silicon carbide wafer. The plurality of silicon carbide devices are electrically, tested to identify ones of the plurality of silicon carbide devices which pass an electrical test. The first contact of the identified ones of the silicon carbide devices are then selectively interconnected. Devices having a plurality of selectively connected silicon carbide devices of the same type are also provided.
摘要翻译：通过在预定图案的碳化硅晶片的至少一部分上形成多个相同类型的碳化硅器件来制造碳化硅器件。碳化硅器件在碳化硅晶片的第一面上具有对应的第一接触。多个碳化硅器件被电学测试以识别通过电测试的多个碳化硅器件中的一个。所识别的碳化硅器件的第一接触然后被选择性地互连。还提供了具有相同类型的多个选择性连接的碳化硅器件的器件。

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