专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

US20060044061A1 Analog delay chain having more uniformly distributed capacitive loads and analog delay cell for use in chain 有权
标题翻译：具有更均匀分布的容性负载的模拟延迟链和用于链中的模拟延迟单元
公开(公告)号：US20060044061A1
公开(公告)日：2006-03-02
申请号：US10928420
申请日：2004-08-27
申请人： Debanjan Mukherjee , Jishnu Bhattacharjee
发明人： Debanjan Mukherjee , Jishnu Bhattacharjee
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F2203/45631 , H03F2203/45638 , H03F2203/45652 , H03F2203/45688 , H03F2203/45712
摘要： A tapped delay chain comprises a plurality of delay cells where each cell has at least two output taps: a primary one for feeding forward a delayed signal to a next cell in the chain, and a secondary output tap for feeding a slightly-differently delayed signal to a multiplier unit so that the slightly-differently delayed signal can be multiplied by a weighting coefficient. The split of output taps in each delay cell allows for a corresponding split of loading capacitance. Each output tap of the delay cell is loaded by a smaller capacitance than it would have had to otherwise drive had the split taps been instead lumped together as a common node. The reduced loading capacitance at each of the split taps allows for a wider frequency response range. The tapped delay chain may be used to form a feed-forward equalizer (FFE) which further comprises an adder, and a plurality of multipliers each respectively receiving a delayed input signal (Sin(delayed)) from a secondary output tap of a respective delay cell in the chain and each outputting a correspondingly delayed and weighted, product signal (Pi) to the adder.
摘要翻译：抽头延迟链包括多个延迟单元，其中每个单元具有至少两个输出抽头：用于将延迟的信号馈送到链中的下一个单元的初级延迟单元，以及用于馈送稍微不同的延迟信号的次级输出抽头到乘法器单元，使得略微不同的延迟信号可以乘以加权系数。每个延迟单元中的输出抽头分开允许相应的负载电容分流。延迟单元的每个输出抽头加载的电容小于如果分裂抽头被集中在一起作为公共节点而不得不以其他方式驱动的电容。每个分接抽头的减小的负载电容允许更宽的频率响应范围。抽头延迟链可用于形成前馈均衡器（FFE），该前馈均衡器还包括加法器和多个乘法器，每个乘法器分别接收延迟的输入信号（（延迟））链中相应的延迟单元的辅助输出抽头，并且每个输出相应的延迟加权乘积信号（Pi）给加法器。

32. 发明授权

US06985036B2 Digitally controlled transconductance cell 有权
标题翻译：数字控制跨导电池
公开(公告)号：US06985036B2
公开(公告)日：2006-01-10
申请号：US10724449
申请日：2003-11-26
申请人： Jishnu Bhattacharjee , Debanjan Mukherjee , Abhijit Phanse
发明人： Jishnu Bhattacharjee , Debanjan Mukherjee , Abhijit Phanse
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F2200/372 , H03F2203/45362 , H03F2203/45466 , H03F2203/45504 , H03F2203/45508 , H03F2203/45631 , H03F2203/45638 , H03F2203/45662 , H03F2203/45731
摘要： A digitally controlled transconductance cell includes a differential transistor pair coupled to load elements (either passive or active with resistive or impedance loads) and a variable bias current source, where the transconductance or gain is digitally varied by changing the aspect ratio of the transistors and the bias current.
摘要翻译：数字控制跨导单元包括耦合到负载元件（无论是具有阻性或阻抗负载的无源或有源）和可变偏置电流源的差分晶体管对，其中跨导或增益通过改变晶体管的纵横比而数字变化，偏置电流。

33. 发明授权

US06940386B2 Multi-layer symmetric inductor 有权
公开(公告)号：US06940386B2
公开(公告)日：2005-09-06
申请号：US10718449
申请日：2003-11-19
申请人： Debanjan Mukherjee , Jishnu Bhattacharjee , Abhijit Phanse
发明人： Debanjan Mukherjee , Jishnu Bhattacharjee , Abhijit Phanse
IPC分类号： H01F17/00 , H01F5/00
CPC分类号： H01F17/0013 , H01F2017/0046 , Y10T29/4902
摘要： An integrated circuit including a differentially excited symmetric microstrip inductor formed over multiple layers while maintaining both electrical and geometrical symmetry.

34. 发明申请

US20050110569A1 DIGITALLY CONTROLLED TRANSCONDUCTANCE CELL 有权
标题翻译：数字控制的交感细胞
公开(公告)号：US20050110569A1
公开(公告)日：2005-05-26
申请号：US10724449
申请日：2003-11-26
申请人： Jishnu Bhattacharjee , Debanjan Mukherjee , Abhijit Phanse
发明人： Jishnu Bhattacharjee , Debanjan Mukherjee , Abhijit Phanse
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F2200/372 , H03F2203/45362 , H03F2203/45466 , H03F2203/45504 , H03F2203/45508 , H03F2203/45631 , H03F2203/45638 , H03F2203/45662 , H03F2203/45731
摘要： A digitally controlled transconductance cell includes a differential transistor pair coupled to load elements (either passive or active with resistive or impedance loads) and a variable bias current source, where the transconductance or gain is digitally varied by changing the aspect ratio of the transistors and the bias current.
摘要翻译：数字控制跨导单元包括耦合到负载元件（无论是具有阻性或阻抗负载的无源或有源）和可变偏置电流源的差分晶体管对，其中跨导或增益通过改变晶体管的纵横比而数字变化，偏置电流。

35. 发明申请

US20050110566A1 Method and apparatus for automatic gain control 有权
标题翻译：自动增益控制的方法和装置
公开(公告)号：US20050110566A1
公开(公告)日：2005-05-26
申请号：US10724444
申请日：2003-11-26
申请人： Jishnu Bhattacharjee , Debanjan Mukherjee , Abhijit Phanse
发明人： Jishnu Bhattacharjee , Debanjan Mukherjee , Abhijit Phanse
IPC分类号： H03G3/00 , H03G3/30 , H03G3/20
CPC分类号： H03G3/30 , H03G3/001
摘要： Systems and methods provide automatic gain control, such as by employing analog and digital techniques. For example, overall gain may be controlled through coarse and fine control signals provided to gain stages, with the overall gain monitored via a power detector circuit.
摘要翻译：系统和方法提供自动增益控制，例如采用模拟和数字技术。例如，可以通过提供给增益级的粗略和精细控制信号来控制总体增益，通过功率检测器电路监测总体增益。

36. 发明申请

US20060082406A1 CONSTRAINED COEFFICIENT ADAPTATION FOR CONTINUOUS-TIME EQUALIZERS 有权
标题翻译：对连续均衡器的约束系数适应
公开(公告)号：US20060082406A1
公开(公告)日：2006-04-20
申请号：US10970471
申请日：2004-10-20
申请人： Debanjan Mukherjee , Jishnu Bhattacharjee , Abhijit Phanse
发明人： Debanjan Mukherjee , Jishnu Bhattacharjee , Abhijit Phanse
IPC分类号： G06F7/44
CPC分类号： H04L25/03885
摘要： A low-voltage constrained coefficient adaptation and multiplication is provided. To provide the constrained coefficient adaptation, an adder adds an adaptive differential control voltage to a forcing differential control voltage to provide an effective coefficient. The adder is configured such that the forcing differential control voltage can prevent the adaptive differential control voltage from producing a sign change in the effective coefficient.
摘要翻译：提供了低压约束系数适应和乘法。为了提供约束系数自适应，加法器将自适应差分控制电压加到强制差分控制电压以提供有效系数。加法器被配置为使得强制差分控制电压可以防止自适应差分控制电压产生有效系数的符号变化。

37. 发明申请

US20060044167A1 Analog signal interpolation 有权
标题翻译：模拟信号插补
公开(公告)号：US20060044167A1
公开(公告)日：2006-03-02
申请号：US11209010
申请日：2005-08-22
申请人： Jishnu Bhattacharjee , Debanjan Mukherjee , Abhijit Phanse
发明人： Jishnu Bhattacharjee , Debanjan Mukherjee , Abhijit Phanse
IPC分类号： H03M3/00
CPC分类号： G06G7/30 , H03F3/45183
摘要： A linear interpolator is provided that includes differential pairs of transistors biased such that a first input voltage may be multiplied by a factor r wherein 0≦r≦1 and such that a second input voltage may be multiplied by the complement factor (1−r). By combining the multiplied input voltages, a linear interpolation is provided based upon the factor r.
摘要翻译：提供了线性内插器，其包括被偏置的差分对晶体管，使得第一输入电压可以乘以因子r，其中0≤r≤1，并且使得第二输入电压可以乘以补码因子（1- r）。通过组合倍增的输入电压，基于因子r提供线性内插。

38. 发明申请

US20050275458A1 Programmable passive inductor 有权
标题翻译：可编程无源电感
公开(公告)号：US20050275458A1
公开(公告)日：2005-12-15
申请号：US11206464
申请日：2005-08-18
申请人： Debanjan Mukherjee , Jishnu Bhattacharjee
发明人： Debanjan Mukherjee , Jishnu Bhattacharjee
IPC分类号： H03F3/45 , H03H11/48
CPC分类号： H03F3/45183 , H03F2203/45638 , H03F2203/45702 , H03F2203/45731
摘要： A programmable passive inductor includes two inductors or coils, each having a self-inductance, magnetically coupled together and having a mutual inductance proportional to a magnetic coupling factor. The relative magnitude of the currents through the two inductors can be dynamically varied, which changes the effective inductance.
摘要翻译：可编程无源电感器包括两个电感器或线圈，每个电感器或线圈都具有磁耦合在一起并具有与磁耦合系数成比例的互感的自感。通过两个电感器的电流的相对幅度可以动态变化，从而改变有效电感。

39. 发明申请

US20050110570A1 Analog signal interpolation 有权
标题翻译：模拟信号插补
公开(公告)号：US20050110570A1
公开(公告)日：2005-05-26
申请号：US10724561
申请日：2003-11-26
申请人： Jishnu Bhattacharjee , Debanjan Mukherjee , Abhijit Phanse
发明人： Jishnu Bhattacharjee , Debanjan Mukherjee , Abhijit Phanse
IPC分类号： G06G7/30 , H03F3/45
CPC分类号： G06G7/30 , H03F3/45183
摘要： A linear interpolator is provided that includes differential pairs of transistors biased such that a first input voltage may be multiplied by a factor r wherein 0≦r≦1 and such that a second input voltage may be multiplied by the complement factor (1-r). By combining the multiplied input voltages, a linear interpolation is provided based upon the factor r.
摘要翻译：提供了线性内插器，其包括被偏置的差分对晶体管，使得第一输入电压可以乘以因子r，其中0≤r≤1，并且使得第二输入电压可以乘以补码因子（1- r）。通过组合倍增的输入电压，基于因子r提供线性内插。

40. 发明申请

US20050110476A1 Trimmable bandgap voltage reference 有权
标题翻译：可调带隙电压参考
公开(公告)号：US20050110476A1
公开(公告)日：2005-05-26
申请号：US10724440
申请日：2003-11-26
申请人： Debanjan Mukherjee , Jishnu Bhattacharjee , Abhijit Phanse
发明人： Debanjan Mukherjee , Jishnu Bhattacharjee , Abhijit Phanse
IPC分类号： G05F3/16 , G05F3/30
CPC分类号： G05F3/30
摘要： A bandgap reference includes a current source providing a current that is proportional to the sum of a first voltage having a positive-to-absolute-temperature (PTAT) temperature dependency and a second voltage having a complementary-to-absolute-temperature (CTAT) dependency. The bandgap reference further includes a variable resistor comprising a fixed resistor that may be selectively combined with one or more of a plurality of selectable resistors, wherein the first voltage is inversely proportional to the resistance of the variable resistor.
摘要翻译：带隙基准包括电流源，其提供与具有正绝对温度（PTAT）温度依赖性的第一电压和具有互补绝对温度（CTAT）的第二电压的和成比例的电流，依赖。带隙参考还包括可变电阻器，其包括可以与多个可选择电阻器中的一个或多个选择性组合的固定电阻器，其中第一电压与可变电阻器的电阻成反比。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式