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31. 发明授权

US06927115B2 Method of fabricating semiconductor integrated circuit 有权
公开(公告)号：US06927115B2
公开(公告)日：2005-08-09
申请号：US10805822
申请日：2004-03-22
申请人： Makoto Yamamoto , Akio Iwabuchi
发明人： Makoto Yamamoto , Akio Iwabuchi
摘要： The lateral pnp transistor encompasses a p-type semiconductor substrate, an n-type first buried region disposed on the semiconductor substrate, an n-type uniform base region disposed on the first buried region, an n-type first plug region disposed in the uniform base region, a p-type first emitter region and a first collector region disposed in and at the top surface of the uniform base region, a graded base region disposed in the uniform base region and a first base contact region disposed in the first plug region. The graded base region encloses the bottom and the side of the first main electrode region. The doping profile in the graded base region intervening between the first emitter region and the first collector region is such that the impurity concentration is gradually decreases towards the second main electrode region from the first main electrode region.

32. 发明申请

US20050104124A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050104124A1
公开(公告)日：2005-05-19
申请号：US10504891
申请日：2003-02-24
申请人： Akio Iwabuchi
发明人： Akio Iwabuchi
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/78 , H01L29/94
CPC分类号： H01L29/0878 , H01L21/823892 , H01L27/092 , H01L29/0615 , H01L29/0634 , H01L29/0692 , H01L29/0847 , H01L29/1083 , H01L29/7816 , H01L29/7835
摘要： A p-channel MOSFET 1 has a buried layer 9 between a substrate 2 and an epitaxial layer 3. The impurity concentration of the buried layer 9 is higher than that of the epitaxial layer 3. As a result, if the p-channel MOSFET 3 and an n-channel MOSFET are fabricated in a single semiconductor substrate and when a voltage is applied between the source electrode 13 and the drain electrode 12, the impurity concentration of the epitaxial layer 3 apparently increases. Thus, the charge balance of the p-channel MOSFET 1 is not lost.
摘要翻译： p沟道MOSFET1在衬底2和外延层3之间具有掩埋层9。掩埋层9的杂质浓度高于外延层3的杂质浓度。结果，如果在单个半导体衬底中制造p沟道MOSFET 3和n沟道MOSFET，并且当在源极13和漏极12之间施加电压时，外延层3的杂质浓度明显地增加因此，p沟道MOSFET 1的电荷平衡不会丢失。

33. 发明授权

US06524949B2 Method of forming low-resistance contact electrodes in semiconductor devices 有权
公开(公告)号：US06524949B2
公开(公告)日：2003-02-25
申请号：US10003192
申请日：2001-10-29
申请人： Shuichi Kaneko , Hironori Aoki , Akio Iwabuchi
发明人： Shuichi Kaneko , Hironori Aoki , Akio Iwabuchi
IPC分类号： H01L214763
CPC分类号： H01L21/76804
摘要： There is formed on a semiconductor substrate a lamination of a first insulating film of nondoped silicon glass or the like and, on this first insulating film, a second insulating film of boron phosphor silicate glass or the like, with a conductor layer between the two insulating films. A hole is first dry-etched in the second insulating film, leaving the substrate surface covered by the first insulating film. Then the second insulating film is heated to a reflow temperature such that the hole is thermally deformed, flaring as it extends away from the insulating film. Then a second hole is dry-etched in the first insulating film through the first recited hole in the second insulating film, with the consequent exposure of the semiconductor surface. Then a contract electrode is fabricated by filling the first and the second hole with an electroconductive material into direct contact with the substrate surface. Being covered by the first insulating film, the substrate surface is not to be contaminated with impurities during the heating of the second insulating film.

34. 发明授权

US09025348B2 Drive circuit 有权
标题翻译：驱动电路
公开(公告)号：US09025348B2
公开(公告)日：2015-05-05
申请号：US13608359
申请日：2012-09-10
申请人： Keiichiro Ozawa , Akio Iwabuchi , Yasushi Tasaka , Ryuichi Furukoshi
发明人： Keiichiro Ozawa , Akio Iwabuchi , Yasushi Tasaka , Ryuichi Furukoshi
IPC分类号： H02M3/335 , H02M1/36 , H02M1/00
CPC分类号： H02M1/36 , H02M3/33523 , H02M2001/0006
摘要： A drive circuit drives a normally-on high-side switch Q1 and a normally-off low-side switch Q2 that form a series circuit connected in parallel with a DC power source. The drive circuit includes a controller 10 that outputs a control signal to turn on/off the high- and low-side switches, a rectifier D2 having a first end connected to a connection point of the high- and low-side switches, a capacitor C2 that is connected to a second end of the rectifier and a first end of the DC power source and serves as a power source for the controller, and a driver (A1, AND1, Q3, Q4) that turns on/off the high- and low-side switches according to the control signal from the controller and a voltage from the capacitor.
摘要翻译：驱动电路驱动形成与直流电源并联连接的串联电路的常开高侧开关Q1和常开低侧开关Q2。驱动电路包括：控制器10，其输出用于接通/关闭高侧和低侧开关的控制信号;整流器D2，其具有连接到高侧开关和低侧开关的连接点的第一端;电容器 C2连接到整流器的第二端和DC电源的第一端，并且用作控制器的电源;以及驱动器（A1，AND1，Q3，Q4）和低侧开关根据来自控制器的控制信号和来自电容器的电压。

35. 发明授权

US08492792B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08492792B2
公开(公告)日：2013-07-23
申请号：US13233392
申请日：2011-09-15
申请人： Akio Iwabuchi , Shuichi Kaneko
发明人： Akio Iwabuchi , Shuichi Kaneko
IPC分类号： H01L29/66
CPC分类号： H01L29/7395 , H01L29/0653 , H01L29/66333
摘要： A manufacturing method of a semiconductor device 10 includes forming a plurality of second conductive second semiconductor regions at specific intervals on one main surface of a first conductive first semiconductor region, the plurality of second conductive second semiconductor regions being opposite to the first conductive first semiconductor region, forming a plurality of the first conductive third semiconductor regions on a main surface of the second semiconductor region, the plurality of the first conductive third regions being separated from each other, forming a plurality of holes at specific intervals on an another main surface which faces the one main surface of the first semiconductor region, the plurality of holes being separated from each other, forming a pair of adjacent second conductive fourth semiconductor regions which are alternately connected at a bottom part of the hole within the first semiconductor region, and burying an electrode within the hole.
摘要翻译：半导体器件10的制造方法包括在第一导电第一半导体区域的一个主表面上以特定间隔形成多个第二导电第二半导体区域，所述多个第二导电第二半导体区域与第一导电第一半导体区域相对在所述第二半导体区域的主表面上形成多个所述第一导电第三半导体区域，所述多个所述第一导电第三区域彼此分离，在另一个主表面上以特定间隔形成多个孔，所述另一个主表面第一半导体区域的一个主表面，多个孔彼此分离，形成一对相邻的第二导电第四半导体区域，其在第一半导体区域内的孔的底部交替连接，并且将电极内孔。

36. 发明授权

US08399913B2 Monolithic integrated circuit 有权
标题翻译：单片集成电路
公开(公告)号：US08399913B2
公开(公告)日：2013-03-19
申请号：US13178988
申请日：2011-07-08
申请人： Mio Suzuki , Akio Iwabuchi
发明人： Mio Suzuki , Akio Iwabuchi
IPC分类号： H01L29/778
CPC分类号： H01L27/0605
摘要： A field-effect semiconductor device such as a HEMT or MESFET is monolithically integrated with a Schottky diode for feedback, regeneration, or protection purposes. The field-effect semiconductor device includes a main semiconductor region having formed thereon a source, a drain, and a gate between the source and the drain. Also formed on the main semiconductor region, preferably between gate and drain, is a Schottky electrode electrically coupled to the source. The Schottky electrode provides a Schottky diode in combination with the main semiconductor region. A current flow is assured from Schottky electrode to drain without interruption by a depletion region expanding from the gate.
摘要翻译：诸如HEMT或MESFET的场效应半导体器件与肖特基二极管单片集成以用于反馈，再生或保护目的。场效应半导体器件包括在源极和漏极之间形成有源极，漏极和栅极的主半导体区域。还形成在主半导体区域上，优选在栅极和漏极之间，是电耦合到源极的肖特基电极。肖特基电极提供与主半导体区域结合的肖特基二极管。从肖特基电极确保电流流动，而不会被从栅极扩大的耗尽区中断地流出。

37. 发明授权

US08217687B2 Capacitive load driver 失效
标题翻译：电容负载驱动
公开(公告)号：US08217687B2
公开(公告)日：2012-07-10
申请号：US12907307
申请日：2010-10-19
申请人： Akio Iwabuchi , Shohei Osaka , Satoru Washiya
发明人： Akio Iwabuchi , Shohei Osaka , Satoru Washiya
IPC分类号： H03B1/00
CPC分类号： H03K17/687 , H03K2217/0036
摘要： A capacitive load driver includes a first switching element whose first end receives positive potential, an EL element arranged between a second end of the first switching element and the ground, a charge collecting capacitor whose first end is connected to a positive electrode terminal of the EL element, a voltage source connected between a second end of the charge collecting capacitor and the ground, and a controller. The controller charges a parasitic capacitance of the EL element and the charge collecting capacitor, and thereafter, applies negative potential from the voltage source to the second end of the charge collecting capacitor. Thereafter, the controller brings the output voltage of the voltage source to ground potential so that the charge collecting capacitor is discharged to charge the EL element. The capacitance of the charge collecting capacitor is set to be sufficiently greater than that of the parasitic capacitance.
摘要翻译：电容性负载驱动器包括第一端接收正电位的第一开关元件，布置在第一开关元件的第二端和地之间的EL元件，其第一端连接到EL的正电极端子的电荷收集电容器元件，连接在电荷收集电容器的第二端和地之间的电压源，以及控制器。控制器对EL元件和电荷收集电容器的寄生电容进行充电，然后从电压源施加负电位到电荷收集电容器的第二端。此后，控制器将电压源的输出电压输入接地电位，使得电荷收集电容器被放电以对EL元件充电。电荷收集电容器的电容被设定为充分大于寄生电容的电容。

38. 发明授权

US08039322B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08039322B2
公开(公告)日：2011-10-18
申请号：US12482060
申请日：2009-06-10
申请人： Akio Iwabuchi , Shuichi Kaneko
发明人： Akio Iwabuchi , Shuichi Kaneko
IPC分类号： H01L21/332
CPC分类号： H01L29/7395 , H01L29/0653 , H01L29/66333
摘要： A manufacturing method of a semiconductor device 10 includes forming a plurality of second conductive second semiconductor regions at specific intervals on one main surface of a first conductive first semiconductor region, the plurality of second conductive second semiconductor regions being opposite to the first conductive first semiconductor region, forming a plurality of the first conductive third semiconductor regions on a main surface of the second semiconductor region, the plurality of the first conductive third regions being separated from each other, forming a plurality of holes at specific intervals on an another main surface which faces the one main surface of the first semiconductor region, the plurality of holes being separated from each other, forming a pair of adjacent second conductive fourth semiconductor regions which are alternately connected at a bottom part of the hole within the first semiconductor region, and burying an electrode within the hole.
摘要翻译：半导体器件10的制造方法包括在第一导电第一半导体区域的一个主表面上以特定间隔形成多个第二导电第二半导体区域，所述多个第二导电第二半导体区域与第一导电第一半导体区域相对在所述第二半导体区域的主表面上形成多个所述第一导电第三半导体区域，所述多个所述第一导电第三区域彼此分离，在另一个主表面上以特定间隔形成多个孔，所述另一个主表面第一半导体区域的一个主表面，多个孔彼此分离，形成一对相邻的第二导电第四半导体区域，其在第一半导体区域内的孔的底部交替连接，并且将电极内孔。

39. 发明申请

US20110204488A1 SEMICONDUCTOR WAFER AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的半导体晶体管和制造方法
公开(公告)号：US20110204488A1
公开(公告)日：2011-08-25
申请号：US13023861
申请日：2011-02-09
申请人： Hironori ITOU , Akio Iwabuchi
发明人： Hironori ITOU , Akio Iwabuchi
IPC分类号： H01L29/06 , H01L21/78
CPC分类号： H01L29/7787 , H01L21/78 , H01L29/2003 , H01L29/452
摘要： A method of manufacturing a semiconductor device includes preparing a semiconductor wafer including a silicon substrate and a laminate having a compound semiconductor layer; etching and removing a part of the laminate in a thickness direction to form trench regions in a grid, each trench region including a plurality of stripe grooves extending in parallel to each other; filling the groove with a material having a lower hardness than the compound semiconductor layer to form a buried region; and dividing the semiconductor wafer into a plurality of chips by dicing using a blade at a dicing line which is defined within the trench region and includes a plurality of the buried regions.
摘要翻译：制造半导体器件的方法包括制备包括硅衬底和具有化合物半导体层的层压体的半导体晶片; 在厚度方向上蚀刻和去除层压体的一部分以在栅格中形成沟槽区域，每个沟槽区域包括彼此平行延伸的多个条纹沟槽; 用具有比化合物半导体层低的硬度的材料填充凹槽以形成掩埋区域; 并且通过在限定在沟槽区域内的切割线上使用刀片进行切割将半导体晶片分成多个芯片，并且包括多个掩埋区域。

40. 发明授权

US07859138B2 Drive circuit 有权
标题翻译：驱动电路
公开(公告)号：US07859138B2
公开(公告)日：2010-12-28
申请号：US11993043
申请日：2006-05-01
申请人： Akio Iwabuchi , Masato Hara
发明人： Akio Iwabuchi , Masato Hara
IPC分类号： H01F27/42
CPC分类号： H02M7/538 , H03K17/063 , H03K2217/0036 , H03K2217/0081
摘要： A drive circuit for a switching circuit has a high-side drive circuit to turn on/off, according to a control signal, a switching element QH arranged on a high side of a DC power source Vin and a low-side drive circuit to turn on/off alternately with the switching element QH according to the control signal a switching element QL arranged on a low side of the DC power source and connected in series with the switching element QH. Ends of an auxiliary power source Vcc1 are connected in series with a switch element Qn1, a capacitor C1, and a switch element Qn2. Both ends of the capacitor C1 are connected in series with a switch element Qp1, a capacitor C2, and a switch element Qp2. A control circuit alternately turns on/off the switch elements Qn1 and Qn2 and the switch elements Qp1 and Qp2. The capacitor C2 provides the high-side drive circuit with source power.
摘要翻译：用于开关电路的驱动电路具有高侧驱动电路，其根据控制信号来接通/断开，布置在直流电源Vin的高侧的开关元件QH和用于转动的低侧驱动电路与开关元件QH交替地与开关元件QH根据控制信号配置在直流电源的低侧并与开关元件QH串联连接的开关元件QL。辅助电源Vcc1的端部与开关元件Qn1，电容器C1和开关元件Qn2串联连接。电容器C1的两端与开关元件Qp1，电容器C2和开关元件Qp2串联连接。控制电路交替地接通/断开开关元件Qn1和Qn2以及开关元件Qp1和Qp2。电容器C2为高边驱动电路提供源电源。

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