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31. 发明申请

US20070085622A1 CONTINUOUS REVERSIBLE GEAR SHIFTING MECHANISM 有权
标题翻译：连续可变齿轮换档机构
公开(公告)号：US20070085622A1
公开(公告)日：2007-04-19
申请号：US11551050
申请日：2006-10-19
申请人： John Wallberg , Robert Staszewski
发明人： John Wallberg , Robert Staszewski
IPC分类号： H03B5/12
CPC分类号： H03L7/093 , H03L7/0991 , H03L7/107 , H03L7/1075 , H03L7/1806
摘要： A novel gear shifting mechanism operative to adjust the loop gain of a phase locked loop (PLL) circuit in a continuous and reversible manner. The loop gain can be increased to widen the bandwidth of the loop and can also be decreased to narrow the loop bandwidth. The mechanism incorporates an α gear shift circuit, a p gear shift circuit and an optional IIR gear shift circuit. The α gear shift circuit comprises a infinite impulse response (IIR) filtering which enables hitless operation of the PLL loop at the occurrence of gear shift events. The α gear shift circuit comprises an accumulator whose output is multiplied by the gain value ρ. The invention enables multiple gear shifts in either positive or negative direction to be achieved by configuring the loop gain variables α and ρ which may be accomplished in software.
摘要翻译：一种新颖的换档机构，可以以连续和可逆的方式调节锁相环（PLL）电路的环路增益。可以增加环路增益以加宽环路的带宽，并且还可以减小环路带宽的窄度。该机构包括一个阿尔法换档电路，一个p换档电路和一个可选的IIR换档电路。阿尔法换档电路包括无限脉冲响应（IIR）滤波，其能够在发生变速事件时实现PLL回路的无中断运行。阿尔法换档电路包括一个累加器，其输出乘以增益值rho。本发明通过配置可以在软件中实现的环路增益变量α和rho来实现正或负方向上的多个换档。

32. 发明申请

US20070085579A1 All digital phase locked loop architecture for low power cellular applications 有权
标题翻译：用于低功率蜂窝应用的所有数字锁相环体系结构
公开(公告)号：US20070085579A1
公开(公告)日：2007-04-19
申请号：US11551150
申请日：2006-10-19
申请人： John Wallberg , Robert Staszewski
发明人： John Wallberg , Robert Staszewski
IPC分类号： H03L7/06 , H03D3/24
CPC分类号： H03L7/08 , H03L2207/50
摘要： A novel mechanism that is operative to observe and compare the differentiated phase of the reference and variable PLL loop signals using a frequency detector. The resultant phase differentiated error is then accumulated to yield the phase error. The operation of the loop with the frequency detector is mathematically equivalent to that of the phase detector. A frequency error accumulator is used to generate the integral of the frequency error. The frequency error accumulator also enables stopping the accumulation of the frequency upon detection of a sufficiently large perturbation, effectively freezing the operation of the loop as subsequent frequency error updates are not accumulated. Upon removal of the phase freeze event, accumulation of the frequency error and consequently normal loop operation resumes.
摘要翻译：一种新颖的机理，用于使用频率检测器观察和比较参考和可变PLL环路信号的微分相位。然后累积产生的相位微分误差以产生相位误差。与频率检测器的环路的操作在数学上等同于相位检测器。频率误差累加器用于产生频率误差的积分。频率误差累加器还能够在检测到足够大的扰动时停止频率的累积，从而有效地冻结环路的操作，因为随后的频率误差更新不被累积。在去除相位冻结事件时，恢复频率误差的累积，从而恢复正常循环操作。

33. 发明申请

US20060164160A1 Technique for improving antialiasing and adjacent channel interference filtering using cascaded passive IIR filter stages combined with direct sampling and mixing 有权
标题翻译：使用级联无源IIR滤波器级与直接采样和混合相结合的改进抗混叠和相邻信道干扰滤波的技术
公开(公告)号：US20060164160A1
公开(公告)日：2006-07-27
申请号：US11388558
申请日：2006-03-24
申请人： Khurram Muhammad , Robert Staszewski , Dirk Leipold
发明人： Khurram Muhammad , Robert Staszewski , Dirk Leipold
IPC分类号： H03K5/00
CPC分类号： H04B1/109 , H03H19/004
摘要： A technique of improving antialiasing and adjacent channel interference filtering uses cascaded passive IIR filter stages combined with direct sampling and mixing. The methodology and related architecture allows for increased passive IIR filtering without necessitating use of amplifier stages.
摘要翻译：改进抗混叠和相邻信道干扰滤波的技术使用级联无源IIR滤波器级与直接采样和混合相结合。该方法和相关架构允许增加无源IIR滤波，而不需要使用放大器级。

34. 发明授权

US10079608B2 Time-to-digital converter and method therefor 有权
公开(公告)号：US10079608B2
公开(公告)日：2018-09-18
申请号：US14343941
申请日：2012-09-10
申请人： Priyanka Kumar , Robert Staszewski , Edoardo Charbon
发明人： Priyanka Kumar , Robert Staszewski , Edoardo Charbon
IPC分类号： H03M1/00 , G01T1/164 , G04F10/00 , G01B11/24 , H04N5/378 , H04N13/00 , H04N13/02
CPC分类号： H03M1/002 , G01B11/24 , G01T1/1647 , G04F10/005 , H04N5/378 , H04N13/20 , H04N2213/001
摘要： Time-to-digital converter system including: an event detector configured for detecting an event and generating an event detection signal upon detection of the event; and a time-to-digital converter coupled or connectable to the event detector and including a fine resolution part configured for counting fine time intervals, organized such that the fine resolution part is activated in response to the event detection signal and deactivated in response to a reference clock. 3D imager including an array of pixels, with in each pixel such a time-to-digital converter system, and further including a reference clock generator.

35. 发明申请

US20140232827A1 TIME-TO-DIGITAL CONVERTER AND METHOD THEREFOR 审中-公开
标题翻译：时间到数字转换器及其方法
公开(公告)号：US20140232827A1
公开(公告)日：2014-08-21
申请号：US14343941
申请日：2012-09-10
申请人： Priyanka Kumar , Robert Staszewski , Edoardo Charbon
发明人： Priyanka Kumar , Robert Staszewski , Edoardo Charbon
IPC分类号： H03M1/00 , H04N13/02 , H04N5/378 , G04F10/00
CPC分类号： H03M1/002 , G01B11/24 , G01T1/1647 , G04F10/005 , H04N5/378 , H04N13/20 , H04N2213/001
摘要： Time-to-digital converter system including: an event detector configured for detecting an event and generating an event detection signal upon detection of the event; and a time-to-digital converter coupled or connectable to the event detector and including a fine resolution part configured for counting fine time intervals, organized such that the fine resolution part is activated in response to the event detection signal and deactivated in response to a reference clock. 3D imager including an array of pixels, with in each pixel such a time-to-digital converter system, and further including a reference clock generator.
摘要翻译：时间到数字转换器系统，包括：事件检测器，被配置为在检测到事件时检测事件并产生事件检测信号; 以及时间数字转换器，其耦合或连接到所述事件检测器，并且包括配置用于对精细时间间隔进行计数的精细分辨率部分，被组织成使得精细分辨率部分响应于事件检测信号被激活并且响应于参考时钟。 3D成像器包括像素阵列，每个像素如时间 - 数字转换器系统，并且还包括参考时钟发生器。

36. 发明申请

US20070085623A1 Gain normalization of a digitally controlled oscillator in an all digital phase locked loop based transmitter 有权
标题翻译：在全数字锁相环的发射机中获得数字控制振荡器的归一化
公开(公告)号：US20070085623A1
公开(公告)日：2007-04-19
申请号：US11550957
申请日：2006-10-19
申请人： Robert Staszewski , John Wallberg
发明人： Robert Staszewski , John Wallberg
IPC分类号： H03L5/00
CPC分类号： H03L7/0991 , H03L7/085 , H03L7/1806 , H03L2207/50 , H04L27/361 , H04L27/368
摘要： A novel mechanism for gain normalization of a digitally controlled oscillator (DCO) in an all digital phase locked loop (ADPLL)-based transmitter that is operative to split the gain normalization multiplication functionality between a modulating path and a PLL loop. The gain normalization of the modulation loop (referred to as modulation path multiplier) comprises a full bit resolution high precision multiplication function. The gain normalization of the PLL loop, on the other hand, is of significantly lower resolution, hence much lower complexity multiplier logic circuitry is required.
摘要翻译：一种用于在基于全数字锁相环（ADPLL）的数字控制振荡器（DCO）中增益归一化的新颖机制，其可操作地在调制路径和PLL环路之间分离增益归一化乘法功能。调制环路（称为调制路径乘法器）的增益归一化包括全位分辨率高精度乘法函数。另一方面，PLL环路的增益归一化具有显着更低的分辨率，因此需要较低复杂度的乘法器逻辑电路。

37. 发明申请

US20060135107A1 Removing close-in interferers through a feedback loop 有权
标题翻译：通过反馈回路消除紧密的干扰源
公开(公告)号：US20060135107A1
公开(公告)日：2006-06-22
申请号：US11339386
申请日：2006-01-25
申请人： Robert Staszewski , Khurram Muhammad , Dirk Leipold
发明人： Robert Staszewski , Khurram Muhammad , Dirk Leipold
IPC分类号： H04B1/10
CPC分类号： H04B1/28 , H04B1/1036
摘要： System and method for elimination of close-in interferers through feedback. A preferred embodiment comprises an interferer predictor (for example, interferer predictor 840) coupled to a digital output of a direct RF radio receiver (for example, radio receiver 800). The interferer predictor predicts the presence of interferers and feeds the information back to a sampling unit (for example, sampling unit 805) through a feedback circuit (for example, feedback unit 845) through the use of charge sharing. The interferers are then eliminated in the sampling unit. Additionally, the number and placement of zeroes in a filter in the sampling unit is increased and changed through the implementation of arbitrary-coefficient finite impulse response filters.
摘要翻译：通过反馈消除接近干扰的系统和方法。优选实施例包括耦合到直接RF无线电接收机（例如，无线电接收机800）的数字输出的干扰源预测器（例如，干扰源预测器840）。干扰源预测器预测干扰源的存在，并且通过使用电荷共享通过反馈电路（例如，反馈单元845）将信息反馈给采样单元（例如，采样单元805）。然后在采样单元中消除干扰源。另外，通过执行任意系数有限脉冲响应滤波器来增加和改变采样单元滤波器中的零数和位置。

38. 发明申请

US20060038624A1 Oscillator system, method of providing a resonating signal and a communications system employing the same 有权
标题翻译：振荡器系统，提供谐振信号的方法和采用该谐振信号的通信系统
公开(公告)号：US20060038624A1
公开(公告)日：2006-02-23
申请号：US10924220
申请日：2004-08-23
申请人： Chih-Ming Hung , Robert Staszewski , Dirk Leipol
发明人： Chih-Ming Hung , Robert Staszewski , Dirk Leipol
IPC分类号： H03B5/12 , H03K3/282
CPC分类号： H03B5/08
摘要： An nth-order oscillator system for providing a resonating signal, a method of generating a resonating signal and a communications system. In one embodiment, the nth-order oscillator system, n being greater than two, includes (1) an amplifier configured to provide an intermediate signal and (2) a feedback loop including an nth-order complex LC tank and configured to generate the resonating signal by feeding back a complex-filtered form of the intermediate signal to the amplifier.
摘要翻译：一种用于提供谐振信号的第n / O级振荡器系统，产生谐振信号的方法和通信系统。在一个实施例中，n大于2的n阶振荡器系统包括（1）被配置为提供中间信号的放大器和（2）包括n + 并且被配置为通过将中间信号的复数滤波形式反馈到放大器来产生谐振信号。

39. 发明申请

US20050264333A1 Efficient pulse amplitude modulation transmit modulation 有权
公开(公告)号：US20050264333A1
公开(公告)日：2005-12-01
申请号：US11195060
申请日：2005-08-02
申请人： Robert Staszewski , Dirk Leipold , Kenneth Maggio
发明人： Robert Staszewski , Dirk Leipold , Kenneth Maggio
IPC分类号： H03F1/02 , H03F1/06 , H03F3/217 , H03K3/00 , H03K3/017 , H03K5/06 , H03K7/02 , H04B1/04
CPC分类号： H03F1/02 , H03F1/0205 , H03F3/217 , H03F3/2171 , H03F3/2176 , H03F2200/331 , H03K5/06 , H03K7/02 , H04B1/0483 , H04B2001/0491
摘要： Efficient PAM transmit modulation is provided by a PAM modulator that includes an oscillator (404) that provides a clock signal, CKV, (408). The clock signal 408 and a delayed version (CKV_DLY) 420 of the clock signal are provided to a logic gate (414). The output of logic gate (414) is used as a power amplifier input signal (PA_IN) for radio frequency power amplifier (416). Depending on the relative time delay of the CKV clock signal (408) and the CKV_DLY delayed clock signal (420), the timing and duty cycle of the logic gate (414) duty cycle can be controlled. The duty cycle or pulse-width variation affects the turn-on time of the power amplifier (416); thereby establishing the RF output amplitude.

40. 发明申请

US20050233725A1 Image reject filtering in a direct sampling mixer 审中-公开
标题翻译：直接采样混频器中的图像抑制滤波
公开(公告)号：US20050233725A1
公开(公告)日：2005-10-20
申请号：US10828386
申请日：2004-04-20
申请人： Khurram Muhammad , Robert Staszewski , Dirk Leipold
发明人： Khurram Muhammad , Robert Staszewski , Dirk Leipold
IPC分类号： H03D7/18 , H03H19/00 , H04B1/16 , H04B1/28
CPC分类号： H03D7/18 , H03H19/004 , H03H2007/0192
摘要： Disclosed are methods, circuits and systems for image reject filtering in a multi-tap direct sampling mixer (MTDSM) of an IF or RF system. Disclosed is the use of rotating capacitors among the in-phase and quadrature branches of a signal processing system. The exchange of information among the branches of the I and Q channels is used in the implementation of a complex filter. Embodiments using cascaded multiple stages of the complex filter to provide higher order complex filters are also disclosed.
摘要翻译：公开了用于IF或RF系统的多抽头直接采样混频器（MTDSM）中的图像抑制滤波的方法，电路和系统。公开了在信号处理系统的同相和正交分支中使用旋转电容器。在I和Q通道的分支之间的信息交换被用于实现复杂的过滤器。还公开了使用复合滤波器的级联多级以提供更高阶复数滤波器的实施例。

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