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31. 发明授权

US08547773B2 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US08547773B2
公开(公告)日：2013-10-01
申请号：US11477714
申请日：2006-06-30
申请人： Takayuki Saiki , Satoru Ito , Masahiko Moriguchi , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise , Junichi Karasawa , Satoru Kodaira , Kazuhiro Maekawa
发明人： Takayuki Saiki , Satoru Ito , Masahiko Moriguchi , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise , Junichi Karasawa , Satoru Kodaira , Kazuhiro Maekawa
IPC分类号： G11C8/00
CPC分类号： G09G3/3674 , G09G3/3685
摘要： An integrated circuit device includes at least one data driver block for driving data lines, a plurality of control transistors TC1 and TC2, each of the control transistors being provided corresponding to each output line of the data driver block and controlled by using a common control signal, and a pad arrangement region in which data driver pads P1 and P2 for electrically connecting the data lines and the output lines QL1 and QL2 of the data driver block are disposed. The control transistors TC1 and TC2 are disposed in the pad arrangement region.
摘要翻译：集成电路装置包括用于驱动数据线的至少一个数据驱动器块，多个控制晶体管TC1和TC2，每个控制晶体管对应于数据驱动器模块的每个输出线提供，并通过使用公共控制信号以及其中设置用于电连接数据线和数据驱动器块的输出线QL1和QL2的数据驱动器焊盘P1和P2的焊盘布置区域。控制晶体管TC1和TC2设置在焊盘布置区域中。

32. 发明授权

US07924202B2 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US07924202B2
公开(公告)日：2011-04-12
申请号：US12389681
申请日：2009-02-20
申请人： Akihiro Fukuzawa , Satoru Ito , Nobuyuki Imai
发明人： Akihiro Fukuzawa , Satoru Ito , Nobuyuki Imai
IPC分类号： H03M1/12
CPC分类号： H03F3/45475 , G01D3/022 , H03F3/45977 , H03F2203/45138 , H03F2203/45212 , H03F2203/45522 , H03G3/30
摘要： An integrated circuit device includes an amplifier circuit that includes first to Nth amplifiers that are cascaded and receives an input signal, an A/D converter that performs an A/D conversion process on a signal amplified by the amplifier circuit, first to Nth D/A converters that are provided corresponding to the first to Nth amplifiers and used to perform an offset adjustment of the first to Nth amplifiers, and a control circuit that sets an offset adjustment of the first to Nth amplifiers using the first to Nth D/A converters and a gain adjustment of the first to Nth amplifiers.
摘要翻译：集成电路装置包括放大电路，其包括级联并接收输入信号的第一至第N放大器，对由放大器电路放大的信号执行A / D转换处理的A / D转换器，第一至第N / A转换器，其对应于第一至第N放大器提供并用于执行第一至第N放大器的偏移调整;以及控制电路，其使用第一至第N D / A转换器设置第一至第N放大器的偏移调整以及第一至第N放大器的增益调整。

33. 发明授权

US07859928B2 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US07859928B2
公开(公告)日：2010-12-28
申请号：US12292996
申请日：2008-12-02
申请人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito
发明人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito
IPC分类号： G11C7/02
CPC分类号： G09G3/3685 , G09G3/20 , G09G3/3611 , G09G5/39 , G09G5/395 , G09G2300/0426 , G09G2310/0218 , G09G2310/027 , G09G2310/0278 , G09G2360/12
摘要： An integrated circuit device having a display memory which stores data for at least one frame from among image information displayed in a display panel which has a plurality of scan lines and a plurality of data lines, the display memory including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and the wordline control circuit selecting an identical wordline N times (N is an integer larger than one) from among the wordlines in one horizontal scan period of the display panel.
摘要翻译：一种具有显示存储器的集成电路装置，该显示存储器从显示在具有多个扫描线和多条数据线的显示面板中的图像信息中存储至少一帧的数据，所述显示存储器包括多个字线，多个位线，多个存储单元和字线控制电路; 并且字线控制电路在显示面板的一个水平扫描周期中从字线中选择相同的字线N次（N是大于1的整数）。

34. 发明授权

US07782694B2 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US07782694B2
公开(公告)日：2010-08-24
申请号：US11477716
申请日：2006-06-30
申请人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa
发明人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa
IPC分类号： G11C7/00
CPC分类号： G09G3/20 , G09G2310/027 , G09G2360/18
摘要： An integrated circuit device includes a display memory and a data read control circuit. The data read control circuit controls data reading so that data of pixels corresponding to a plurality of signal lines is read out by N-time reading in one horizontal scan period of a display panel (N is an integer larger than 1). The display memory includes a plurality of sense amplifier cells respectively connected with a plurality of bitlines. L sense amplifier cells (L is an integer larger than 1) respectively connected with the bitlines of L memory cells adjacent in a first direction (wordline direction) in which wordlines extend are disposed along a second direction (bitline direction) in which the bitlines extend.
摘要翻译：集成电路装置包括显示存储器和数据读取控制电路。数据读取控制电路控制数据读取，使得通过在显示面板的一个水平扫描周期（N是大于1的整数）中的N次读取来读出与多条信号线相对应的像素的数据。显示存储器包括分别与多个位线连接的多个读出放大器单元。分别与字线延伸的第一方向（字线方向）相邻的L个存储单元的位线分别连接的L个读出放大器单元（L是大于1的整数）沿着位线延伸的第二个方向（位线方向）。

35. 发明授权

US07613066B2 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US07613066B2
公开(公告)日：2009-11-03
申请号：US11477719
申请日：2006-06-30
申请人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa
发明人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa
IPC分类号： G11C8/00
CPC分类号： G09G3/3685 , G09G2300/0426 , G09G2310/0218 , G09G2310/027 , G09G2360/12
摘要： In an integrated circuit device, a data line driver block which drives data lines of a display panel based on data supplied from a RAM block from which data is read N times (N is an integer larger than one) in one horizontal scan period 1H of the display panel includes first to N-th divided data line driver blocks disposed along a first direction in which bitlines extend. When data supplied from the RAM block is M bits (M is an integer larger than 1) and grayscale of a pixel corresponding to the data line is G bits, each of the first to N-th divided data line driver blocks includes (M/G) (multiple of three) data line driver cells which drive (M/G) data lines. (M/3G) R data line driver cells are provided in a first subdivided driver, (M/3G) G data line driver cells are provided in a second subdivided driver, and (M/3G) B data line driver cells are provided in a third subdivided driver.
摘要翻译：在集成电路装置中，数据线驱动器模块，其基于从RAM数据块提供的数据驱动显示面板的数据线，数据被读取N次（N为大于1的整数）N 显示面板包括沿位线延伸的第一方向设置的第一至第N分割数据线驱动器块。当从RAM块提供的数据是M位（M是大于1的整数）并且与数据线相对应的像素的灰度级是G位时，第一至第N划分数据线驱动器块中的每一个包括（M / G）（三个的三个）数据线驱动器单元驱动（M / G）数据线。（M / 3G）R数据线驱动器单元设置在第一细分驱动器中，（M / 3G）G数据线驱动器单元设置在第二细分驱动器中，并且（M / 3G）B数据线驱动器单元设置在第三个细分驱动程序。

36. 发明授权

US07522441B2 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US07522441B2
公开(公告)日：2009-04-21
申请号：US11270553
申请日：2005-11-10
申请人： Takashi Kumagai , Hisanobu Ishiyama , Kazuhiro Maekawa , Satoru Ito , Takashi Fujise , Junichi Karasawa , Satoru Kodaira
发明人： Takashi Kumagai , Hisanobu Ishiyama , Kazuhiro Maekawa , Satoru Ito , Takashi Fujise , Junichi Karasawa , Satoru Kodaira
IPC分类号： G11C5/06
CPC分类号： G09G3/2096 , G09G3/3666 , G09G3/3688 , G09G3/3696 , G09G2310/027 , G09G2310/0289 , G09G2310/0297 , G09G2360/18
摘要： An integrated circuit device including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include a high-speed interface circuit block HB which transfers data through a serial bus using differential signals, and a circuit block other than HB. The high-speed interface circuit block HB is disposed as an Mth circuit block CBM (2≦M≦N−1) of the circuit blocks CB1 to CBN.
摘要翻译：一种集成电路装置，包括沿着第一方向D1设置的第一至第N电路块CB1至CBN，当第一方向D1是从集成电路器件的第一侧朝向与第一侧相反的第三侧的方向时，第一侧为短边，当第二方向D2为从集成电路器件的第二侧向与第二侧相反的第四侧的方向时，第二侧为长边。电路块CB1至CBN包括通过使用差分信号的串行总线传送数据的高速接口电路块HB以及HB以外的电路块。高速接口电路块HB被布置为电路块CB1至CBN的第M个电路块CBM（2 <= M <= N-1）。

37. 发明授权

US07436378B2 LED-switching controller and LED-switching control method 有权
标题翻译： LED开关控制器和LED开关控制方式
公开(公告)号：US07436378B2
公开(公告)日：2008-10-14
申请号：US10957387
申请日：2004-10-02
申请人： Satoru Ito , Seijun Nishimura , Toshiya Fujiyama
发明人： Satoru Ito , Seijun Nishimura , Toshiya Fujiyama
IPC分类号： G09G3/32 , G09G5/00 , G09G3/10
CPC分类号： H05B33/0815 , H05B33/0827 , Y02B20/347
摘要： An LED terminal monitoring circuit detects an LED at the lowest potential among a plurality of parallel-connected LEDs. An analog signal selecting circuit gives a signal indicating the voltage of the detected LED to a boosting circuit. The boosting circuit performs a boosting operation on the basis of the condition of the detected LED at the lowest voltage and, consequently, a voltage sufficient for driving the LEDs in a current-control mode can be applied to all the LEDs. Signal lines not connected to LEDs are excluded from objects of a LED-switching control operation.
摘要翻译： LED端子监视电路检测多个并联LED的最低电位的LED。模拟信号选择电路将检测到的LED的电压指示给升压电路。升压电路基于检测到的LED处于最低电压的状态来执行升压操作，因此可以对所有LED施加足以驱动LED的电流控制模式的电压。未连接到LED的信号线被排除在LED开关控制操作的对象之外。

38. 发明申请

US20080237406A1 COMMUNICATION SYSTEM IN TRAINS 有权
标题翻译：火车通讯系统
公开(公告)号：US20080237406A1
公开(公告)日：2008-10-02
申请号：US12019048
申请日：2008-01-24
申请人： Nao Saito , Setsuo Arita , Satoru Ito , Kazunori Ayabe , Yukio Sagawa
发明人： Nao Saito , Setsuo Arita , Satoru Ito , Kazunori Ayabe , Yukio Sagawa
IPC分类号： B61L25/02 , B61D37/00
CPC分类号： B61D49/00 , B61L15/0036 , B61L15/009
摘要： A communication system in trains comprises a control data communication device 400 and an image data communication device 300 installed in each of the cars. The control data communication device 400 transmits train operation information, train location information, control instructions of train-mounted apparatuses, and the like. The image data communication device 300 transmits image information such as moving images and still images, audio information such as in-train announcement, textual information for caption display, and operation log information of apparatuses, which form the contents, to a display unit 200 installed in each of the cars and to apparatuses 500 such as a telephone. The display unit 200 switches the display on the screen in accordance with train control information transmitted from the control data communication device 400 through the image data communication device 300.
摘要翻译：列车中的通信系统包括控制数据通信设备400和安装在每个轿厢中的图像数据通信设备300。控制数据通信装置400发送列车运行信息，列车位置信息，列车装置的控制指令等。图像数据通信装置300将形成内容的诸如运动图像和静止图像的图像信息，诸如列车内公告的音频信息，字幕显示的文本信息和装置的操作日志信息发送到安装的显示单元200 在每个汽车中以及诸如电话的设备500。显示单元200根据从控制数据通信设备400通过图像数据通信设备300发送的列车控制信息来切换屏幕上的显示。

39. 发明申请

US20070188426A1 LED driver circuit 审中-公开
标题翻译： LED驱动电路
公开(公告)号：US20070188426A1
公开(公告)日：2007-08-16
申请号：US11351925
申请日：2006-02-10
申请人： Satoru Ito , Seijun Nishimura
发明人： Satoru Ito , Seijun Nishimura
IPC分类号： G09G3/32
CPC分类号： G09G3/3291
摘要： Disclosed is an LED driver circuit that can suitably detect a minimum voltage and can be produced at low cost. A selector circuit is comprised of a comparator C, an inverter I and analogue switches. A minimum voltage selecting circuit can be constructed by causing the selector circuit and a circuit constructed in the same manner as the selector circuit is done, to be combined with each other. Therefore, the minimum voltage selecting circuit can be comprised of active devices that comprise only p-MOSFETs and n-MOSFETs. Moreover, as a semiconductor process structure, there may be employed a so-called single WELL structure in which a WELL is not formed in another WELL. The LED driver circuit is formed at low cost.
摘要翻译：公开了可以适当地检测最低电压并且可以以低成本生产的LED驱动器电路。选择器电路由比较器C，反相器I和模拟开关组成。可以通过使选择器电路和以与选择器电路相同的方式构成的电路彼此组合来构造最小电压选择电路。因此，最小电压选择电路可以由仅包括p-MOSFET和n-MOSFET的有源器件组成。此外，作为半导体工艺结构，可以采用所谓的单个WELL结构，其中在另一个WELL中不形成WELL。 LED驱动器电路以低成本形成。

40. 发明申请

US20070016700A1 Integrated circuit device and electronic instrument 审中-公开
标题翻译：集成电路器件和电子仪器
公开(公告)号：US20070016700A1
公开(公告)日：2007-01-18
申请号：US11477669
申请日：2006-06-30
申请人： Satoru Kodaira , Noboru Itomi , Takashi Kumagai , Satoru Ito , Junichi Karasawa , Shuji Kawaguchi
发明人： Satoru Kodaira , Noboru Itomi , Takashi Kumagai , Satoru Ito , Junichi Karasawa , Shuji Kawaguchi
IPC分类号： G06F5/00 , G06F3/00
CPC分类号： G06F7/76 , G11C7/1006 , G11C7/1051
摘要： An integrated circuit device has a data memory including a memory cell array which includes a plurality of wordlines, a plurality of bitlines, and a plurality of memory cells, and a memory output circuit. The data read order in the memory cell array corresponding to the arrangement of the bitlines differs from the data output order from the memory output circuit. The integrated circuit device includes a rearrangement interconnect region in a region of the memory output circuit. The rearrangement interconnect region rearranges data input in the data read order using interconnects and outputs the data in the data output order.
摘要翻译：集成电路装置具有包括存储单元阵列的数据存储器，该存储单元阵列包括多个字线，多个位线和多个存储单元，以及存储器输出电路。与位线布置对应的存储单元阵列中的数据读取顺序与存储器输出电路的数据输出顺序不同。集成电路装置包括在存储器输出电路的区域中的重排互连区域。重新布置互连区域使用互连重新排列以数据读取顺序输入的数据，并以数据输出顺序输出数据。

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