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31. 发明授权

US06255202B1 Damascene T-gate using a spacer flow 有权
标题翻译：大马士革T型门采用间隔流
公开(公告)号：US06255202B1
公开(公告)日：2001-07-03
申请号：US09619836
申请日：2000-07-20
申请人： Christopher F. Lyons , Ramkumar Subramanian , Bhanwar Singh , Marina Plat
发明人： Christopher F. Lyons , Ramkumar Subramanian , Bhanwar Singh , Marina Plat
IPC分类号： H01L213205
CPC分类号： H01L29/66583 , H01L21/28114 , H01L21/28123 , H01L21/76807 , H01L29/4238 , H01L29/4925
摘要： A method for fabricating a T-gate structure is provided. A structure is provided that has a silicon layer having a gate oxide layer, a polysilicon layer over the gate oxide layer and an insulating layer over the gate oxide layer. An opening is formed extending partially into the insulating layer. The opening in the insulating layer extends from a top surface of the insulating layer to a first depth. Spacers are then formed on the sides of the opening. The opening is then extended in the insulating layer from the first depth to a second depth. The opening is wider from the top surface of the insulating layer to the first depth than the opening is from the first depth to the second depth. The spacers are then removed from the opening. The opening is then filled with a conductive material to form a T-gate structure.
摘要翻译：提供了一种制造T型栅结构的方法。提供一种结构，其具有硅层，该硅层具有栅极氧化物层，栅极氧化物层上的多晶硅层和栅极氧化物层上的绝缘层。形成部分地延伸到绝缘层中的开口。绝缘层中的开口从绝缘层的顶表面延伸到第一深度。然后在开口的两侧形成隔板。然后将开口在绝缘层中从第一深度延伸到第二深度。开口从绝缘层的顶表面到比第一深度从第一深度到第二深度的第一深度更宽。然后将隔离物从开口中取出。然后用导电材料填充开口以形成T形栅结构。

32. 发明授权

US06165695A Thin resist with amorphous silicon hard mask for via etch application 有权
标题翻译：具有非晶硅硬掩模的薄抗蚀剂，用于通孔蚀刻应用
公开(公告)号：US06165695A
公开(公告)日：2000-12-26
申请号：US203150
申请日：1998-12-01
申请人： Chih Yuh Yang , Christopher F. Lyons , Harry J. Levinson , Khanh B. Nguyen , Fei Wang , Scott A. Bell
发明人： Chih Yuh Yang , Christopher F. Lyons , Harry J. Levinson , Khanh B. Nguyen , Fei Wang , Scott A. Bell
IPC分类号： H01L21/027 , H01L21/033 , H01L21/311 , H01L21/768 , G03C5/00
CPC分类号： H01L21/31144 , H01L21/0276 , H01L21/0332 , H01L21/0338 , H01L21/76816 , Y10S430/168
摘要： A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and an amorphous silicon layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the amorphous silicon layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the amorphous silicon layer. The first etch step includes an etch chemistry that is selective to the amorphous silicon layer over the ultra-thin photoresist layer and the dielectric layer. The amorphous silicon layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.
摘要翻译：提供一种形成通孔结构的方法。在该方法中，在覆盖第一金属层的抗反射涂层（ARC）层上形成电介质层; 并且在该电介质层上形成非晶硅层。在非晶硅层上形成超薄光致抗蚀剂层，并用短波长辐射对超薄光致抗蚀剂层进行构图，以限定通孔的图案。在第一蚀刻步骤期间，将图案化超薄光致抗蚀剂层用作掩模，以将通孔图案转印到非晶硅层。第一蚀刻步骤包括对超薄光致抗蚀剂层和介电层上的非晶硅层有选择性的蚀刻化学品。在第二蚀刻步骤期间，非晶硅层用作硬掩模，以通过蚀刻介电层的部分形成对应于通孔图案的接触孔。

33. 发明授权

US6114235A Multipurpose cap layer dielectric 失效
标题翻译：多功能盖层电介质
公开(公告)号：US6114235A
公开(公告)日：2000-09-05
申请号：US924571
申请日：1997-09-05
申请人： David K. Foote , Minh Van Ngo , Christopher F. Lyons , Fei Wang , Raymond T. Lee , William G. En , Susan H. Chen , Darin A. Chan
发明人： David K. Foote , Minh Van Ngo , Christopher F. Lyons , Fei Wang , Raymond T. Lee , William G. En , Susan H. Chen , Darin A. Chan
IPC分类号： H01L21/027 , H01L21/311 , H01L21/314 , H01L21/768 , H01L21/44
CPC分类号： H01L21/0276 , H01L21/31144 , H01L21/76802 , H01L21/76829 , H01L21/7684 , H01L21/3145 , Y10S438/945
摘要： A multipurpose cap layer serves as a bottom anti-reflective coating (BARC) during the formation of a resist mask, a hardmask during subsequent etching processes, a hardened surface during subsequent deposition and planarization processes, and optionally as a diffusion barrier to mobile ions from subsequently deposited materials.
摘要翻译：在形成抗蚀剂掩模，后续蚀刻工艺期间的硬掩模，随后的沉积和平坦化工艺期间的硬化表面，以及任选地作为对移动离子的扩散阻挡层，多功能盖层用作底部抗反射涂层（BARC）随后沉积材料。

34. 发明授权

US5744537A Antireflective coating films 失效
标题翻译：顶级抗反射涂膜
公开(公告)号：US5744537A
公开(公告)日：1998-04-28
申请号：US863678
申请日：1997-05-27
申请人： William R. Brunsvold , George J. Hefferon , Christopher F. Lyons , Wayne M. Moreau , Robert L. Wood
发明人： William R. Brunsvold , George J. Hefferon , Christopher F. Lyons , Wayne M. Moreau , Robert L. Wood
IPC分类号： G03F7/11 , C08L27/12 , G03F7/00 , G03F7/09 , H01L21/027 , H01L21/30
CPC分类号： G03F7/091 , G03F7/092 , Y10T428/3154
摘要： Enhanced fidelity of pattern transfer of aqueous developable photoresist compositions is achieved with top antirefective coatings which are fluorine-containing and have a refractive index approximately equal to the square root of the underlying photoresist and which are removable in the developer for the photoresist.
摘要翻译：水性可显影光致抗蚀剂组合物的图案转印的增强的保真度是通过含氟的顶部抗有效涂层实现的，其折射率近似等于下面光致抗蚀剂的平方根，并且可在光致抗蚀剂的显影剂中除去。

35. 发明授权

US5482817A Mid and deep-uv antireflection coatings and methods for use thereof 失效
标题翻译：中，深紫外防反射涂层及其使用方法
公开(公告)号：US5482817A
公开(公告)日：1996-01-09
申请号：US315318
申请日：1994-09-29
申请人： Robert R. Dichiara , Christopher F. Lyons , Ratnasabapathy Sooriyakumaran , Gary T. Spinillo , Kevin M. Welsh , Robert L. Wood
发明人： Robert R. Dichiara , Christopher F. Lyons , Ratnasabapathy Sooriyakumaran , Gary T. Spinillo , Kevin M. Welsh , Robert L. Wood
IPC分类号： G03F7/11 , G03F7/09 , H01L21/027 , H01L21/30 , G03C5/00
CPC分类号： G03F7/091 , Y10S522/904
摘要： An antireflective coating composition (ARC) for use with chemically amplified photoresist compositions comprising a polymer composition which is highly absorbent to mid and deep UV radiation, which is substantially inert to contact reactions with a chemically amplified photoresist composition, and which is insoluble in the developer for the chemically amplified photoresist composition.
摘要翻译：一种用于化学放大光致抗蚀剂组合物的抗反射涂料组合物（ARC），其包含对中和深紫外线辐射具有高吸收性的聚合物组合物，其对于与化学放大的光致抗蚀剂组合物的接触反应基本上是惰性的，并且不溶于显影剂用于化学放大光致抗蚀剂组合物。

36. 发明授权

US07052921B1 System and method using in situ scatterometry to detect photoresist pattern integrity during the photolithography process 有权
标题翻译：使用原位散射法在光刻过程中检测光致抗蚀剂图案完整性的系统和方法
公开(公告)号：US07052921B1
公开(公告)日：2006-05-30
申请号：US10934192
申请日：2004-09-03
申请人： Marina V. Plat , Bhanwar Singh , Calvin T. Gabriel , Christopher F. Lyons , Scott A. Bell , Ramkumar Subramanian , Srikanteswara Dakshina-Murthy
发明人： Marina V. Plat , Bhanwar Singh , Calvin T. Gabriel , Christopher F. Lyons , Scott A. Bell , Ramkumar Subramanian , Srikanteswara Dakshina-Murthy
IPC分类号： H01L21/66
CPC分类号： G03F7/70625 , G03F7/70608 , H01L22/12
摘要： The present invention uses in situ scatterometry to determine if a defect (e.g., photoresist erosion, photoresist bending and pattern collapse) is present on a wafer. In one embodiment, in situ scatterometry is used to detect a pattern integrity defect associated with the layer of photoresist. In situ scatterometry produces diffraction data associated with the thickness of the photoresist patterned mask. This data is compared to a model of diffraction data associated with a suitable photoresist thickness. If the measured diffraction data is within an acceptable range, the next step of the photolithography process is carried out. However, if the measured thickness is outside of the suitable range, a defect is detected, and the wafer may be sent for re-working or re-patterned prior to main etch, thereby preventing unnecessary wafer scrap. Another aspect of the present invention allows for a feedback control mechanism to alter a physical parameter of the photolithographic process based upon the in situ scatterometry measurements.
摘要翻译：本发明使用原位散射法来确定晶片上是否存在缺陷（例如，光致抗蚀剂侵蚀，光致抗蚀剂弯曲和图案崩溃）。在一个实施例中，原位散射法用于检测与光致抗蚀剂层相关联的图案完整性缺陷。原位散射法产生与光致抗蚀剂图案掩模的厚度相关的衍射数据。将该数据与与合适的光致抗蚀剂厚度相关联的衍射数据的模型进行比较。如果测量的衍射数据在可接受的范围内，则进行光刻工艺的下一步骤。然而，如果测量的厚度在合适的范围之外，则检测到缺陷，并且可以在主蚀刻之前将晶片发送用于再加工或重新图案化，从而防止不必要的晶片废料。本发明的另一方面允许反馈控制机制基于原位散射测量来改变光刻工艺的物理参数。

37. 发明授权

US06900124B1 Patterning for elliptical Vss contact on flash memory 有权
标题翻译：闪存上的椭圆形Vss接触图案化
公开(公告)号：US06900124B1
公开(公告)日：2005-05-31
申请号：US10654739
申请日：2003-09-03
申请人： Hung-eil Kim , Anna Minvielle , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
发明人： Hung-eil Kim , Anna Minvielle , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
IPC分类号： H01L21/4763 , H01L21/768 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L21/76802 , H01L27/115
摘要： A method of forming a contact in a flash memory device is disclosed. The method increases the depth of focus margin and the overlay margin between the contact and the stacked gate layers. A plurality of stacked gate layers are formed on a semiconductor substrate, wherein each stacked gate layer extends in a predefined direction and is substantially parallel to other stacked gate layers. An interlayer insulating layer is deposited over the plurality of stacked gate layers, and a contact hole is patterned between a first stacked gate layer of the plurality of stacked gate layers and a second stacked gate layer of the plurality of stacked gate layers. The contact hole is formed in an elongated shape, wherein a major axis of the contact hole is substantially parallel to the stacked gate layers. A conductive layer is deposited in the contact hole and excess conductive material is removed.
摘要翻译：公开了一种在闪速存储器件中形成触点的方法。该方法增加了接触和层叠栅极层之间的焦距裕度和覆盖边缘的深度。在半导体衬底上形成多个层叠的栅极层，其中每个堆叠的栅极层沿预定的方向延伸并且基本上平行于其它堆叠的栅极层。层叠绝缘层沉积在多个堆叠的栅极层上，并且在多个堆叠的栅极层的第一堆叠的栅极层和多个堆叠的栅极层的第二叠层栅极层之间形成接触孔。接触孔形成为细长形状，其中接触孔的长轴基本上平行于堆叠的栅极层。导电层沉积在接触孔中，去除过量的导电材料。

38. 发明授权

US06878961B2 Photosensitive polymeric memory elements 有权
标题翻译：光敏聚合物记忆元件
公开(公告)号：US06878961B2
公开(公告)日：2005-04-12
申请号：US10951370
申请日：2004-09-28
申请人： Christopher F. Lyons , Ramkumar Subramanian , Mark S. Chang
发明人： Christopher F. Lyons , Ramkumar Subramanian , Mark S. Chang
IPC分类号： G11C11/56 , G11C13/02 , H01L27/28 , H01L35/24
CPC分类号： H01L27/285 , B82Y10/00 , G11C11/5664 , G11C13/0014 , G11C13/0016 , G11C13/025 , G11C13/04 , Y10S977/943
摘要： A method of making organic memory cells made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer that contains a photosensitive compound. The organic semiconductor layer is formed into memory cells using patterning techniques.
摘要翻译：公开了一种由在两个电极之间具有可控导电介质的两个电极制成的有机存储单元的方法。可控导电介质包含含有光敏化合物的有机半导体层。使用图案化技术将有机半导体层形成为存储单元。

39. 发明授权

US06864024B1 Real-time control of chemically-amplified resist processing on wafer 失效
标题翻译：化学放大抗蚀剂加工在晶圆上的实时控制
公开(公告)号：US06864024B1
公开(公告)日：2005-03-08
申请号：US10302225
申请日：2002-11-22
申请人： Christopher F. Lyons , Bharath Rangarajan
发明人： Christopher F. Lyons , Bharath Rangarajan
IPC分类号： A61N5/00 , G03C5/00 , G03F7/038 , G03F7/039 , G03F9/00
CPC分类号： G03F7/0382 , G03F7/0392
摘要： One aspect of the present invention relates to a system and method for controlling environmental acid scavengers in real time during pattern exposure of a chemically amplified resist-clad wafer. The system includes a semiconductor wafer comprising a chemically amplified resist layer formed over a substrate layer, wherein a first portion of the resist layer has been removed to expose an area of the substrate layer in order to form a probe area; an exposure system programmed to implement an exposure process to transfer a device pattern onto at least a second portion of the resist layer; and a monitoring system adapted to detect chemical signals about the probe area in order to control the integrity of the resist layer during the exposure process. The method involves feeding data back to the on-going exposure process in order to effect an immediate change in the process.
摘要翻译：本发明的一个方面涉及在化学放大的抗蚀剂包覆晶片的图案曝光期间实时控制环境酸清除剂的系统和方法。该系统包括半导体晶片，其包括在衬底层上形成的化学放大抗蚀剂层，其中已除去抗蚀剂层的第一部分以暴露衬底层的区域以形成探针区域; 曝光系统被编程为实现曝光过程以将装置图案转印到抗蚀剂层的至少第二部分上; 以及适于检测关于探针区域的化学信号以便在曝光过程期间控制抗蚀剂层的完整性的监测系统。该方法涉及将数据馈送回正在进行的曝光过程，以便立即改变过程。

40. 发明授权

US06849530B2 Method for semiconductor gate line dimension reduction 失效
公开(公告)号：US06849530B2
公开(公告)日：2005-02-01
申请号：US10334337
申请日：2002-12-30
申请人： Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Christopher F. Lyons
发明人： Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Christopher F. Lyons
IPC分类号： H01L21/28 , H01L21/4763
CPC分类号： H01L21/28123
摘要： To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.

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