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31. 发明申请

US20080270953A1 IC CHIP AT-FUNCTIONAL-SPEED TESTING WITH PROCESS COVERAGE EVALUATION 有权
标题翻译： IC芯片功能快速测试与过程覆盖评估
公开(公告)号：US20080270953A1
公开(公告)日：2008-10-30
申请号：US11741164
申请日：2007-04-27
申请人： Eric A. Foreman , Gary D. Grise , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Eric A. Foreman , Gary D. Grise , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/10
摘要： Methods, systems and program products for evaluating an IC chip are disclosed. In one embodiment, the method includes running a statistical static timing analysis (SSTA) of a full IC chip design; creating at-functional-speed test (AFST) robust paths for an IC chip, the created robust paths representing a non-comprehensive list of AFST robust paths for the IC chip; and re-running the SSTA with the SSTA delay model setup based on the created robust paths. A process coverage is calculated for evaluation from the SSTA runnings; and a particular IC chip is evaluated based on the process coverage.
摘要翻译：公开了用于评估IC芯片的方法，系统和程序产品。在一个实施例中，该方法包括运行全IC芯片设计的统计静态时序分析（SSTA）; 创建用于IC芯片的功能速度测试（AFST）鲁棒路径，所创建的鲁棒路径表示IC芯片的AFST鲁棒路径的非全面列表; 并基于创建的鲁棒路径，使用SSTA延迟模型设置重新运行SSTA。计算过程覆盖率用于从SSTA运行中进行评估; 并且基于处理覆盖来评估特定的IC芯片。

32. 发明授权

US08707233B2 Systems and methods for correlated parameters in statistical static timing analysis 失效
标题翻译：统计静态时序分析中相关参数的系统和方法
公开(公告)号：US08707233B2
公开(公告)日：2014-04-22
申请号：US13190083
申请日：2011-07-25
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031 , G06F17/5081
摘要： Systems and methods for accommodating correlated parameters in SSTA are provided. The method includes determining a correlation between at least two parameters. The method further includes calculating a new parameter or a new parameter set based on the correlation between the at least two parameters. The method further includes performing the SSTA such that the new parameter or the new parameter set is propagated into the SSTA. The method further includes projecting slack using the correlation between the at least two parameters and using a processor.
摘要翻译：提供了适应SSTA相关参数的系统和方法。该方法包括确定至少两个参数之间的相关性。该方法还包括基于至少两个参数之间的相关性计算新参数或新参数集。该方法还包括执行SSTA，使得新参数或新参数集传播到SSTA中。该方法还包括使用至少两个参数之间的相关性并使用处理器来投影松弛。

33. 发明授权

US08141014B2 System and method for common history pessimism relief during static timing analysis 有权
标题翻译：静态时序分析中共同历史悲观缓解的系统和方法
公开(公告)号：US08141014B2
公开(公告)日：2012-03-20
申请号：US12538229
申请日：2009-08-10
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Kerim Kalafala , Jeffrey P. Soreff
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Kerim Kalafala , Jeffrey P. Soreff
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A system and method for adjustment of modeled timing data variation as a function of past state and/or switching history during static timing analysis. One illustrative embodiment may include inputting and asserting at least one of initial signal history bound and explicit device history bound constraints for at least one signal of a circuit design and evaluating for a segment processed during a forward propagation of block based static timing analysis whether any input signal to a current segment has a bounded history, at least one of propagated and asserted. The method may further include evaluating for the segment whether history bounds are downstream from a gating restriction, and processing a next segment until there are no further segments.
摘要翻译：一种用于在静态时序分析期间调整作为过去状态和/或切换历史的函数的建模定时数据变化的系统和方法。一个说明性实施例可以包括输入和断言用于电路设计的至少一个信号的初始信号历史约束和显式设备历史约束约束中的至少一个，并且针对在基于块的静态时序分析的正向传播期间处理的段来评估是否有任何输入对当前段的信号具有有界历史，至少一个传播和断言。该方法可以进一步包括评估该段是否历史边界是在门控限制的下游，以及处理下一个段，直到没有进一步的段。

34. 发明授权

US08086988B2 Chip design and fabrication method optimized for profit 有权
标题翻译：芯片设计和制造方法优化利润
公开(公告)号：US08086988B2
公开(公告)日：2011-12-27
申请号：US12467326
申请日：2009-05-18
申请人： Nathan Buck , Howard H. Chen , James P. Eckhardt , Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Susan K. Lichtensteiger , Chandramouli Visweswariah , Tad J. Wilder
发明人： Nathan Buck , Howard H. Chen , James P. Eckhardt , Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Susan K. Lichtensteiger , Chandramouli Visweswariah , Tad J. Wilder
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031
摘要： Disclosed is a computer-implemented method for designing a chip to optimize yielding parts in different bins as a function of multiple diverse metrics and further to maximize the profit potential of the resulting chip bins. The method separately calculates joint probability distributions (JPD), each JPD being a function of a different metric (e.g., performance, power consumption, etc.). Based on the JPDs, corresponding yield curves are generated. A profit function then reduces the values of all of these metrics (e.g., performance values, power consumption values, etc.) to a common profit denominator (e.g., to monetary values indicating profit that may be associated with a given metric value). The profit function and, more particularly, the monetary values can be used to combine the various yield curves into a combined profit-based yield curve from which a profit model can be generated. Based on this profit model, changes to the chip design can be made in order to optimize yield as a function of all of the diverse metrics (e.g., performance, power consumption, etc.) and further to maximize the profit potential of the resulting chips.
摘要翻译：公开了一种计算机实现的方法，用于设计芯片以优化不同仓中的产量部分作为多个不同度量的函数，并进一步最大化所得到的芯片仓的利润潜力。该方法分别计算联合概率分布（JPD），每个JPD是不同度量（例如，性能，功耗等）的函数。基于JPD，生成相应的收益率曲线。利润函数然后将所有这些度量（例如，绩效值，功耗值等）的值减小到公共利润分母（例如，指示可能与给定度量值相关联的利润的货币值）。更具体地说，利润函数，尤其是货币价值可用于将各种收益率曲线组合成基于利润的收益率曲线，从中可以生成利润模型。基于这种利润模型，可以对芯片设计进行改变，以便根据所有不同的指标（例如性能，功耗等）来优化产量，并进一步最大化所得芯片的利润潜力。

35. 发明授权

US07870525B2 Slack sensitivity to parameter variation based timing analysis 有权
标题翻译：对基于参数变化的时序分析的松弛敏感性
公开(公告)号：US07870525B2
公开(公告)日：2011-01-11
申请号：US12122451
申请日：2008-05-16
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.
摘要翻译：公开了一种用于改进IC设计的方法，系统和程序产品，其优先考虑根据其故障概率导致校正的松弛故障系数。通过确定的一组独立参数，当参数变化时，通过注意时序上的差异，通常在端点松弛时，对每个参数执行灵敏度分析。对于每个独立参数重复此步骤。然后从参考松弛和每个定时端点的松弛的灵敏度计算失效系数，并且确定至少一个定时端点是否失败阈值测试。然后将失败的定时终点根据其故障系数进行优先级修改。所需的总运行次数是一次运行，用作参考运行，每个参数再运行一次运行。

36. 发明授权

US07716616B2 Slack sensitivity to parameter variation based timing analysis 失效
标题翻译：对基于参数变化的时序分析的松弛敏感性
公开(公告)号：US07716616B2
公开(公告)日：2010-05-11
申请号：US11930924
申请日：2007-10-31
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.
摘要翻译：公开了一种用于改进IC设计的方法，系统和程序产品，其优先考虑根据其故障概率导致校正的松弛故障系数。通过确定的一组独立参数，当参数变化时，通过注意时序上的差异，通常在端点松弛时，对每个参数执行灵敏度分析。对于每个独立参数重复此步骤。然后从参考松弛和每个定时端点的松弛的灵敏度计算失效系数，并且确定至少一个定时端点是否失败阈值测试。然后将失败的定时终点根据其故障系数进行优先级修改。所需的总运行次数是一次运行，用作参考运行，每个参数再运行一次运行。

37. 发明授权

US07181711B2 Prioritizing of nets for coupled noise analysis 失效
标题翻译：耦合噪声分析网优先级
公开(公告)号：US07181711B2
公开(公告)日：2007-02-20
申请号：US10908101
申请日：2005-04-27
申请人： Eric A. Foreman , Peter A. Habitz , Gregory M. Schaeffer
发明人： Eric A. Foreman , Peter A. Habitz , Gregory M. Schaeffer
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A system and method of performing microelectronic chip timing analysis, wherein the method comprises identifying failing timing paths in a chip; prioritizing the failing timing paths in the chip according to a size of random noise events occurring in each timing path; attributing a slack credit statistic for all but highest order random noise events occurring in each timing path; and calculating a worst case timing path scenario based on the prioritized failing timing paths and the slack credit statistic. Preferably, the random noise events comprise non-clock events. Moreover, the random noise events may comprise victim/aggressor net groups belonging to different regularity groups. Preferably, the size of random noise events comprises coupled noise delta delays due to the random noise events occurring in the chip.
摘要翻译：一种执行微电子芯片定时分析的系统和方法，其中所述方法包括识别芯片中的故障定时路径; 根据每个定时路径中发生的随机噪声事件的大小对芯片中的故障定时路径进行优先级排序; 归因于每个定时路径中发生的所有但最高阶随机噪声事件的松弛信用统计; 以及基于优先顺序的故障定时路径和松弛信用统计量来计算最坏情况的定时路径情景。优选地，随机噪声事件包括非时钟事件。此外，随机噪声事件可以包括属于不同规则组的受害者/侵略者网络组。优选地，由于芯片中发生的随机噪声事件，随机噪声事件的大小包括耦合的噪声增量延迟。

38. 发明授权

US08448110B2 Method to reduce delay variation by sensitivity cancellation 失效
标题翻译：通过灵敏度消除来减少延迟变化的方法
公开(公告)号：US08448110B2
公开(公告)日：2013-05-21
申请号：US12625139
申请日：2009-11-24
申请人： Peter A. Habitz , Eric A. Foreman , Gustavo E. Tellez
发明人： Peter A. Habitz , Eric A. Foreman , Gustavo E. Tellez
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5031 , G06F2217/12 , G06F2217/84 , Y02P90/265
摘要： A method receives an initial circuit design. The circuit design includes at least one path having at least one beginning point comprising a source, at least one ending point comprising a sink, and one or more circuit elements between the source and the sink. The method evaluates timing performance parameter sensitivities to manufacturing variations of each of the elements to identify how much each element will increase or decrease the timing performance parameter of the path for each change in each manufacturing variable associated with manufacturing the elements. Further, the method alters the elements within the path until elements that produce positive changes to the timing performance parameter for a given manufacturing variable change approximately equals (in magnitude) elements that produce negative changes to the timing performance parameter for the given manufacturing variable change, to produce an altered circuit design.
摘要翻译：一种方法接收初始电路设计。该电路设计包括至少一个路径，该至少一个路径具有包括源的至少一个起始点，包括宿的至少一个终点以及源和宿之间的一个或多个电路元件。该方法评估每个元件的制造变化的时序性能参数灵敏度，以识别每个元件将增加或减少与制造元件相关联的每个制造变量中的每个变化的路径的时序性能参数。此外，该方法改变路径内的元素，直到产生对于给定制造变量的定时性能参数的正变化的元素大致等于（在大小上）元素，该元素对于给定的制造变量变化而对定时性能参数产生负变化，以产生改变的电路设计。

39. 发明申请

US20100180243A1 Method of Performing Timing Analysis on Integrated Circuit Chips with Consideration of Process Variations 有权
标题翻译：对考虑过程变化的集成电路芯片执行时序分析的方法
公开(公告)号：US20100180243A1
公开(公告)日：2010-07-15
申请号：US12354306
申请日：2009-01-15
申请人： Debjit Sinha , Eric A. Foreman , Peter A. Habitz , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
发明人： Debjit Sinha , Eric A. Foreman , Peter A. Habitz , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method for verifying whether a circuit meets timing constraints by performing an incremental static timing analysis in which slack is represented by a distribution that includes sensitivities to various process variables. The slack at an endpoint is computed by propagating the arrival times and required arrival times of paths leading up to the endpoint. The computation of arrival and required arrival times needs the computation of delays of individual gate and wire segments in each path that leads to the endpoint. The mixed mode adds a deterministic timing to the statistical timing (DSTA+SSTA).
摘要翻译：一种用于通过执行增量静态时序分析来验证电路是否满足时序约束的方法，其中松弛由包括对各种过程变量的灵敏度的分布表示。通过传播到达端点的路径的到达时间和所需到达时间来计算端点的松弛度。到达和到达时间的计算需要计算通向端点的每个路径中各个门和线段的延迟。混合模式为统计时间（DSTA + SSTA）增加了一个确定性时序。

40. 发明授权

US07750648B2 Method to quickly estimate inductance for timing models 有权
标题翻译：快速估计定时模型电感的方法
公开(公告)号：US07750648B2
公开(公告)日：2010-07-06
申请号：US12059275
申请日：2008-03-31
申请人： Eric A. Foreman , Peter A. Habitz , Mark R. Lasher , William J. Livingstone , Gregory M. Schaeffer
发明人： Eric A. Foreman , Peter A. Habitz , Mark R. Lasher , William J. Livingstone , Gregory M. Schaeffer
IPC分类号： G01R27/00
CPC分类号： G01R27/2611 , G01R27/28 , G06F17/5036 , G06F2217/84
摘要： A method of estimating an inductance delay includes determining a resistance-capacitance (RC) delay with resistances and capacitances of a network and estimating an inductance delay of the network by determining a propagation delay of an electromagnetic (EM) field across wires of the network. Additionally, the method includes determining if the RC delay is below a specified threshold and adding the estimated inductance delay to the RC delay to determine a total time to propagate voltage swings through the network if the RC delay is below the specified threshold.
摘要翻译：估计电感延迟的方法包括通过确定网络的电线（EM）场的传播延迟来确定网络的电阻和电容的电阻 - 电容（RC）延迟并估计网络的电感延迟。此外，该方法包括确定RC延迟是否低于指定的阈值，并将估计的电感延迟与RC延迟相加，以确定如果RC延迟低于指定阈值，则传播通过网络的电压摆幅的总时间。

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