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    • 39. 发明授权
    • Analog PLL clock recovery circuit and a LAN transceiver employing the
same
    • 模拟PLL时钟恢复电路和采用该模拟PLL时钟恢复电路的LAN收发器
    • US5448598A
    • 1995-09-05
    • US88008
    • 1993-07-06
    • Nariman YousefiBenjamin E. NiseKelly P. McClellan
    • Nariman YousefiBenjamin E. NiseKelly P. McClellan
    • H03L7/089H04L7/033H04L7/00H03D3/24H04L25/36H04L25/40
    • H04L7/033H03L7/0898
    • A VSLI transceiver chip incorporating an improved analog PLL circuit for recovering a digital clock signal from a digital data signal having pulse widths which may vary during each data cycle. The analog PLL clock recovery circuit comprises a phase detector, a gain control circuit, a variable current charge pump, a loop filter and a variable frequency oscillator. The phase detection means for detecting, during each data cycle, the phase error between the digital data signal and recovered digital clock signal, and produces first end second digital control pulse signals in response to the detection of the phase error. The gain control means produces third and fourth digital control pulse signals during each data cycle. The value of the third and fourth control pulse signals during each data cycle depends on the value of the digital data signal, the value of the recovered clock signal, and the value of the second digital control pulse signal during the data cycle, and the change in value of the third and fourth control pulse signals is responsive to the change in the value of the recovered digital clock signal. The variable current charge pump receives the first and second digital control pulse signals. The recovered digital clock signal is produced by variable frequency oscillator, having a clock frequency proportional to the produced analog control signal.
    • VSLI收发器芯片包含改进的模拟PLL电路,用于从具有在每个数据周期期间可能变化的脉冲宽度的数字数据信号中恢复数字时钟信号。 模拟PLL时钟恢复电路包括相位检测器,增益控制电路,可变电流电荷泵,环路滤波器和可变频率振荡器。 相位检测装置,用于在每个数据周期期间检测数字数据信号与恢复的数字时钟信号之间的相位误差,并响应于相位误差的检测产生第一端第二数字控制脉冲信号。 增益控制装置在每个数据周期期间产生第三和第四数字控制脉冲信号。 在每个数据周期期间,第三和第四控制脉冲信号的值取决于数据数据信号的值,恢复的时钟信号的值和数据周期期间的第二数字控制脉冲信号的值, 第三和第四控制脉冲信号的输入值响应于恢复的数字时钟信号的值的变化。 可变电流电荷泵接收第一和第二数字控制脉冲信号。 恢复的数字时钟信号由可变频率振荡器产生,具有与所产生的模拟控制信号成比例的时钟频率。
    • 40. 发明授权
    • Power dissipation management for wired transceivers
    • 有线收发器的功耗管理
    • US08520553B2
    • 2013-08-27
    • US12944355
    • 2010-11-11
    • Nariman YousefiScott Powell
    • Nariman YousefiScott Powell
    • H04L12/28
    • H04L12/12Y02D50/20Y02D50/40Y02D50/42
    • A system, method and apparatus for reducing a power consumed by a physical layer device (PHY). A length of a cable connecting the PHY to a link partner is determined. Based on the length, power provided to one or more components of the PHY, or any portion thereof, is reduced. The power provided is reduced while maintaining a level of reliability specified by a protocol governing operation of the PHY. The length can be determined using time-domain reflectometry (TDR) techniques. Any portion of an echo cancellation filter, a crosstalk filter, an equalizer, a precoder, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a forward error correction (FEC) decoder and/or an FEC coder can be powered-down or power-optimized to reduce the overall power consumed by the PHY. The protocol governing operation of the PHY can be IEEE 802.3.
    • 一种用于减少物理层设备(PHY)消耗的功率的系统,方法和装置。 确定将PHY连接到链路伙伴的电缆的长度。 基于长度,减少了提供给PHY的一个或多个组件或其任何部分的功率。 提供的功率降低,同时保持由控制PHY的操作的协议规定的可靠性水平。 可以使用时域反射(TDR)技术确定长度。 回波消除滤波器,串扰滤波器,均衡器,预编码器,模数转换器(ADC),数模转换器(DAC),前向纠错(FEC)解码器和/ 或者可以对FEC编码器进行掉电或功率优化,以减少PHY消耗的总体功耗。 控制PHY的操作的协议可以是IEEE 802.3。