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31. 发明申请

US20120068774A1 Amplitude Control for Oscillator 失效
标题翻译：振荡器振幅控制
公开(公告)号：US20120068774A1
公开(公告)日：2012-03-22
申请号：US12886719
申请日：2010-09-21
申请人： Zhiqin Chen , Nam V. Dang , Nan Chen , Thuan Ly
发明人： Zhiqin Chen , Nam V. Dang , Nan Chen , Thuan Ly
IPC分类号： H03L5/00
CPC分类号： H03L5/00 , H03B5/36 , H03L3/00
摘要： An amplitude control circuit includes a pair of peak detectors. The pair of peak detectors are responsive to a voltage reference generator. The amplitude control circuit is configured to be responsive to an oscillating signal of a crystal oscillator and configured to generate a control signal to control an amplitude of the oscillating signal.
摘要翻译：振幅控制电路包括一对峰值检测器。一对峰值检测器响应于电压参考发生器。幅度控制电路被配置为响应于晶体振荡器的振荡信号，并被配置为产生控制信号以控制振荡信号的振幅。

32. 发明申请

US20110235449A1 Dual Sensing Current Latched Sense Amplifier 审中-公开
标题翻译：双感应电流锁定检测放大器
公开(公告)号：US20110235449A1
公开(公告)日：2011-09-29
申请号：US12731623
申请日：2010-03-25
申请人： Nan Chen , Ritu Chaba
发明人： Nan Chen , Ritu Chaba
IPC分类号： G11C7/06
CPC分类号： G11C7/00 , G11C7/065 , G11C7/08 , G11C7/12
摘要： A sense amplifier and method thereof are provided. The sense amplifier includes first and second transistors coupled to first and second bit lines, respectively. The first and second transistors are configured to connect the first and second bit lines to a differential amplifier during a first state (e.g., when a differential voltage is present on the first and second bit lines and prior to a sense signal transition) and to isolate the first and second bit lines from the differential amplifier during a second state (e.g., after the sense signal transition). The sense amplifier further includes a third transistor configured to deactivate the differential amplifier during the first state and configured to activate the differential amplifier during the second state.
摘要翻译：提供了一种读出放大器及其方法。读出放大器分别包括耦合到第一和第二位线的第一和第二晶体管。第一和第二晶体管被配置为在第一状态期间（例如，当差分电压存在于第一和第二位线上并且在感测信号转换之前）时将第一和第二位线连接到差分放大器并且隔离在第二状态（例如，在感测信号转换之后）来自差分放大器的第一和第二位线。读出放大器还包括第三晶体管，其被配置为在第一状态期间去激活差分放大器并且被配置为在第二状态期间激活差分放大器。

33. 发明授权

US08000165B2 Self reset clock buffer in memory devices 有权
公开(公告)号：US08000165B2
公开(公告)日：2011-08-16
申请号：US12207011
申请日：2008-09-09
申请人： Changho Jung , Nan Chen , Zhiqin Chen
发明人： Changho Jung , Nan Chen , Zhiqin Chen
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/225 , H03K3/0372
摘要： A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of at least one of the logic gates is coupled to an input of at least one of the logic gates. The cross-coupled logic circuit is coupled to an input for accepting a clock signal. The memory device also includes a clock driver operable to generate a clock signal from the output of the cross-coupled logic circuit. A feedback loop from the clock signal to the cross-coupled logic circuit controls the cross-coupled logic circuit. A buffer circuit including a tri-state inverter is coupled to the clock signal to maintain the clock signal while avoiding contention with the clock generator. The memory device is enabled by a chip select signal.

34. 发明授权

US07881137B2 Read assist for memory circuits with different precharge voltage levels for bit line pair 有权
标题翻译：对位线对具有不同预充电电压电平的存储电路的读辅助
公开(公告)号：US07881137B2
公开(公告)日：2011-02-01
申请号：US12256569
申请日：2008-10-23
申请人： Nan Chen , Ritu Chaba
发明人： Nan Chen , Ritu Chaba
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C7/12 , G11C11/417
摘要： A method increases stability of a memory circuit by pre-charging at least one bit line of the memory circuit to a first voltage, pre-charging at least one other bit line of the memory circuit to a second voltage, and equalizing charge across the bit lines so that the bit lines are pre-charged with a third voltage.
摘要翻译：一种方法通过将存储器电路的至少一个位线预充电到第一电压来增加存储器电路的稳定性，将存储器电路的至少一个其它位线预充电到第二电压，并且平衡位上的电荷使得位线被预充电第三电压。

35. 发明授权

US07872930B2 Testing a memory device having field effect transistors subject to threshold voltage shifts caused by bias temperature instability 有权
标题翻译：测试具有由偏置温度不稳定性引起的阈值电压偏移的场效应晶体管的存储器件
公开(公告)号：US07872930B2
公开(公告)日：2011-01-18
申请号：US12121560
申请日：2008-05-15
申请人： Nan Chen , Sian-Yee Sean Lee , Seong-Ook Jung , Zhongze Wang
发明人： Nan Chen , Sian-Yee Sean Lee , Seong-Ook Jung , Zhongze Wang
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/10 , G11C29/12005
摘要： A supply voltage is set for a memory device at a first supply voltage level. Test data is written to the memory device at the first supply voltage level in response to setting the supply voltage. The supply voltage is decreased for the memory device to a second supply voltage level below the first supply voltage level in response to writing the test data. The test data is read from the memory device at the second supply voltage level in response to decreasing the supply voltage. The supply voltage is increased for the memory device to a third supply voltage level above the second supply voltage level in response to reading the test data. The test data is read from the memory device at the third supply voltage level in response to increasing the supply voltage. The test data written to the memory device at the first supply voltage level is compared to the test data read from the memory device at the third supply voltage level in response to reading the test data from the memory device at the third supply voltage level.
摘要翻译：在第一电源电压电平下为存储器件设置电源电压。响应于设置电源电压，以第一电源电压电平将测试数据写入存储器件。响应于写入测试数据，存储器件的电源电压降低到低于第一电源电压电平的第二电源电压电平。响应于降低电源电压，在第二电源电压电平下从存储器件读取测试数据。响应于读取测试数据，存储器件的电源电压增加到高于第二电源电压电平的第三电源电压电平。响应于增加电源电压，在第三电源电压电平下从存储器件读取测试数据。响应于以第三电源电压从存储器件读取测试数据，将以第一电源电压电平写入存储器件的测试数据与从第三电源电压电平读出的测试数据进行比较。

36. 发明申请

US20100226191A1 Leakage Reduction in Memory Devices 有权
标题翻译：内存设备中的泄漏减少
公开(公告)号：US20100226191A1
公开(公告)日：2010-09-09
申请号：US12397142
申请日：2009-03-03
申请人： Changho Jung , Nan Chen , Cheng Zhong , Zhiqin Chen
发明人： Changho Jung , Nan Chen , Cheng Zhong , Zhiqin Chen
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C7/00 , G11C7/22 , G11C8/08 , G11C11/4094 , G11C11/413 , G11C2207/2227 , H03K19/0016
摘要： A memory device includes a core array that includes memory cells. The memory device also includes a headswitch coupled to the core array and a positive supply voltage. The headswitch reduces leakage current from the core array by disconnecting the core array from the positive supply voltage. Additionally, head switches are added for pre-charge devices to further reduce leakage current.
摘要翻译：存储器件包括包括存储器单元的核心阵列。存储器件还包括耦合到芯阵列的头灯和正电源电压。磁头开关通过将磁芯阵列与正电源电压断开来减少来自磁芯阵列的漏电流。另外，增加头开关用于预充电器件，以进一步减少泄漏电流。

37. 发明申请

US20100195366A1 Reducing Leakage Current in a Memory Device 有权
标题翻译：降低存储器件中的泄漏电流
公开(公告)号：US20100195366A1
公开(公告)日：2010-08-05
申请号：US12364105
申请日：2009-02-02
申请人： Nan Chen , Mehdi Hamidi Sani , Ritu Chaba
发明人： Nan Chen , Mehdi Hamidi Sani , Ritu Chaba
IPC分类号： G11C17/00 , G11C5/14 , G11C7/00
CPC分类号： G11C17/18 , G11C5/14 , G11C5/147 , G11C7/12
摘要： Memory devices and methods of reducing leakage current therein are disclosed. The memory device includes a memory core array including a plurality of bitlines, and peripheral logic configured to interface with the memory core array. The memory device further includes a footswitch configured to isolate the peripheral logic from a ground voltage, and a headswitch configured to isolate a precharge current path from the plurality of bit lines of the memory core array. Leakage current within the memory device may be reduced via the isolation provided by the footswitch and the headswitch.
摘要翻译：公开了减少漏电流的存储器件和方法。存储器件包括包括多个位线的存储器核心阵列和被配置为与存储器核心阵列接口的外围逻辑。存储器件还包括被配置为将外围逻辑与接地电压隔离的脚踏开关和被配置为将预充电电流路径与存储器核心阵列的多个位线隔离的头开关。通过脚踏开关和头开关提供的隔离可以减小存储器件内的泄漏电流。

38. 发明申请

US20100046276A1 Systems and Methods for Handling Negative Bias Temperature Instability Stress in Memory Bitcells 审中-公开
标题翻译：处理负偏压的系统和方法存储器位单元中的温度不稳定性应力
公开(公告)号：US20100046276A1
公开(公告)日：2010-02-25
申请号：US12194342
申请日：2008-08-19
申请人： Nan Chen , Cheng Zhong , Ritu Chaba
发明人： Nan Chen , Cheng Zhong , Ritu Chaba
IPC分类号： G11C11/00 , G11C5/14 , G11C7/00
CPC分类号： G11C7/1006 , G11C7/04 , G11C7/20 , G11C7/22 , G11C11/413
摘要： A system and method reduce stress caused by NBTI effects by determining if a trigger event has occurred and if so inverting all input data values to the memory and all output data values from the memory during a period of time defined by the determined trigger event. In one embodiment, the trigger event is an alternate memory power-up.
摘要翻译：系统和方法通过确定触发事件是否已经发生，并且如果在所确定的触发事件所定义的时间段期间将所有输入数据值反转到存储器和所有输出数据值，从而减少由NBTI效应引起的应力。在一个实施例中，触发事件是备用存储器加电。

39. 发明申请

US20090285044A1 TESTING A MEMORY DEVICE HAVING FIELD EFFECT TRANSISTORS SUBJECT TO THRESHOLD VOLTAGE SHIFTS CAUSED BY BIAS TEMPERATURE INSTABILITY 有权
标题翻译：测试具有由偏置温度不稳定性引起的阈值电压变化的场效应晶体管的存储器件
公开(公告)号：US20090285044A1
公开(公告)日：2009-11-19
申请号：US12121560
申请日：2008-05-15
申请人： Nan Chen , Sian-Yee Sean Lee , Seong-Ook Jung , Zhongze Wang
发明人： Nan Chen , Sian-Yee Sean Lee , Seong-Ook Jung , Zhongze Wang
IPC分类号： F21V29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/10 , G11C29/12005
摘要： A supply voltage is set for a memory device at a first supply voltage level. Test data is written to the memory device at the first supply voltage level in response to setting the supply voltage. The supply voltage is decreased for the memory device to a second supply voltage level below the first supply voltage level in response to writing the test data. The test data is read from the memory device at the second supply voltage level in response to decreasing the supply voltage. The supply voltage is increased for the memory device to a third supply voltage level above the second supply voltage level in response to reading the test data. The test data is read from the memory device at the third supply voltage level in response to increasing the supply voltage. The test data written to the memory device at the first supply voltage level is compared to the test data read from the memory device at the third supply voltage level in response to reading the test data from the memory device at the third supply voltage level.
摘要翻译：在第一电源电压电平下为存储器件设置电源电压。响应于设置电源电压，以第一电源电压电平将测试数据写入存储器件。响应于写入测试数据，存储器件的电源电压降低到低于第一电源电压电平的第二电源电压电平。响应于降低电源电压，在第二电源电压电平下从存储器件读取测试数据。响应于读取测试数据，存储器件的电源电压增加到高于第二电源电压电平的第三电源电压电平。响应于增加电源电压，在第三电源电压电平下从存储器件读取测试数据。响应于以第三电源电压从存储器件读取测试数据，将以第一电源电压电平写入存储器件的测试数据与从第三电源电压电平读出的测试数据进行比较。

40. 发明授权

US09916904B2 Reducing leakage current in a memory device 有权
公开(公告)号：US09916904B2
公开(公告)日：2018-03-13
申请号：US12364105
申请日：2009-02-02
申请人： Nan Chen , Mehdi Hamidi Sani , Ritu Chaba
发明人： Nan Chen , Mehdi Hamidi Sani , Ritu Chaba
IPC分类号： G11C7/12 , G11C17/18 , G11C5/14
CPC分类号： G11C17/18 , G11C5/14 , G11C5/147 , G11C7/12
摘要： Memory devices and methods of reducing leakage current therein are disclosed. The memory device includes a memory core array including a plurality of bitlines, and peripheral logic configured to interface with the memory core array. The memory device further includes a footswitch configured to isolate the peripheral logic from a ground voltage, and a headswitch configured to isolate a precharge current path from the plurality of bit lines of the memory core array. Leakage current within the memory device may be reduced via the isolation provided by the footswitch and the headswitch.

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