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31. 发明申请

US20060195734A1 Semiconductor memory device and stress testing method thereof 有权
标题翻译：半导体存储器件及其应力测试方法
公开(公告)号：US20060195734A1
公开(公告)日：2006-08-31
申请号：US11349091
申请日：2006-02-08
申请人： Kayoko Shibata , Hiroaki Ikeda
发明人： Kayoko Shibata , Hiroaki Ikeda
IPC分类号： G01R31/28
CPC分类号： G11C29/12 , G01R31/2856 , G01R31/31721 , G11C29/12005 , G11C29/1201 , H01L25/18 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/16145 , H01L2225/06565 , H01L2924/0002 , H01L2924/15311 , H01L2224/05552
摘要： A semiconductor memory device includes a core chip having at least memory cells formed in the core chip, an interface chip having at least peripheral circuits of the memory cells formed in the interface chip, and an external terminal group. The external terminal group includes at least a core power supply terminal that is connected to an internal circuit of the core chip without being connected to an internal circuit of the interface chip, and an interface power supply terminal that is connected to an internal circuit of the interface chip without being connected to the internal circuit of the core chip. With this arrangement, mutually different operation voltages that are optimum for both chips can be given to these chips.
摘要翻译：半导体存储器件包括至少具有形成在芯片芯片中的存储器单元的芯片芯片，至少具有形成在接口芯片中的存储单元的外围电路的接口芯片和外部端子组。外部端子组至少包括与芯片的内部电路连接而不连接到接口芯片的内部电路的核心电源端子，以及连接到内部电路的内部电路的接口电源端子接口芯片不连接到核心芯片的内部电路。利用这种布置，可以给这些芯片提供对两个芯片最佳的相互不同的操作电压。

32. 发明授权

US06986072B2 Register capable of corresponding to wide frequency band and signal generating method using the same 有权
公开(公告)号：US06986072B2
公开(公告)日：2006-01-10
申请号：US10206822
申请日：2002-07-29
申请人： Yoji Nishio , Seiji Funaba , Kayoko Shibata , Toshio Sugano , Hiroaki Ikeda , Takuo Iizuka , Masayuki Sorimachi
发明人： Yoji Nishio , Seiji Funaba , Kayoko Shibata , Toshio Sugano , Hiroaki Ikeda , Takuo Iizuka , Masayuki Sorimachi
IPC分类号： G11C7/08 , G06F1/06 , G06F1/10
CPC分类号： G11C5/04 , G11C5/00 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/222 , H03L7/0814
摘要： A maximum value of the number of mounted memory devices is assumed, and a value of an external delay replica is fixed and set. A desired frequency band is divided into a plurality of sub-frequency bands, and delay times of an output buffer and an internal delay replica are switched and used every sub-frequency band, thereby setting an actual maximum value and an actual minimum value to the internal delay replica. A selecting pin can select the delay time in the internal delay replica. Thus, it is possible to sufficiently ensure a set-up time and a hold time of an internal clock signal generated by a delay locked loop circuit in the latch operation in a register within a desired frequency band and with a permittable number of memory devices, irrespective of the frequency level and the number of mounted memory devices.

33. 发明授权

US06707726B2 Register without restriction of number of mounted memory devices and memory module having the same 有权
标题翻译：在不限制安装的存储器件的数量和具有相同的存储器模块的情况下进行注册
公开(公告)号：US06707726B2
公开(公告)日：2004-03-16
申请号：US10206823
申请日：2002-07-29
申请人： Yoji Nishio , Seiji Funaba , Kayoko Shibata , Toshio Sugano , Hiroaki Ikeda , Takuo Iizuka , Masayuki Sorimachi
发明人： Yoji Nishio , Seiji Funaba , Kayoko Shibata , Toshio Sugano , Hiroaki Ikeda , Takuo Iizuka , Masayuki Sorimachi
IPC分类号： G11C700
CPC分类号： G11C7/109 , G11C7/1078 , G11C7/1087 , G11C8/06 , G11C2207/107
摘要： First and second pre-processing flip-flops latch a command/address signal inputted to a register by a clock having a frequency of ½ of an external clock signal and an inverse clock thereof. Thus, the command/address signal is decomprossed to a set of signals which temporarily has two times. For example, one of the set of signals has only data contents of an odd-th command/address signal, and the other has only data contents of an even-th command/address signal. Since the set of signals has twice periods of the command/address signal, first and second post-processing flip-flop can latch signals in accordance with an internal clock signal generated by a delay locked loop circuit in a state in which a set-up time and a hold time are sufficiently assured.
摘要翻译：第一和第二预处理触发器通过具有外部时钟信号的1/2的频率的时钟及其反时钟来锁存输入到寄存器的命令/地址信号。因此，命令/地址信号被分解成一组暂时具有两次的信号。例如，该组信号之一仅具有奇数命令/地址信号的数据内容，而另一个仅具有偶数个命令/地址信号的数据内容。由于该组信号具有两个命令/地址信号的周期，所以第一和第二后处理触发器可以根据由延迟锁定环电路产生的内部时钟信号来锁存信号，时间和保持时间充分确保。

34. 发明授权

US08350389B2 Semiconductor device and information processing system including the same 有权
标题翻译：半导体装置和信息处理系统也包括在内
公开(公告)号：US08350389B2
公开(公告)日：2013-01-08
申请号：US12923789
申请日：2010-10-07
申请人： Satoshi Itaya , Kayoko Shibata , Shoji Azuma , Akira Ide
发明人： Satoshi Itaya , Kayoko Shibata , Shoji Azuma , Akira Ide
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L21/76898 , H01L21/563 , H01L23/3128 , H01L23/481 , H01L23/49811 , H01L24/03 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L2224/0401 , H01L2224/0603 , H01L2224/13022 , H01L2224/1308 , H01L2224/13082 , H01L2224/13099 , H01L2224/1403 , H01L2224/16145 , H01L2224/73203 , H01L2225/06513 , H01L2225/06541 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01037 , H01L2924/01051 , H01L2924/01055 , H01L2924/01074 , H01L2924/01076 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/30105 , H01L2924/3011 , H01L2924/00014
摘要： A semiconductor device includes a plurality of core chips and an interface chip that controls the core chips. Each of the core chips and the interface chip includes plural through silicon vias that penetrate a semiconductor substrate and plural pads respectively connected to the through silicon vias. The through silicon vias include a through silicon via of a power source system to which a power source potential or a ground potential is supplied, and a through silicon via of a signal system to which various signals are supplied. Among the pads, at least an size of a pad connected to the through silicon via of the power source system is larger than a size of a pad connected to the through silicon via of the signal system. Therefore, a larger parasitic capacitance can be secured.
摘要翻译：半导体器件包括多个核心芯片和控制芯片芯片的接口芯片。芯片芯片和接口芯片中的每一个都包括穿透半导体衬底的多个穿过硅通孔和分别连接到通孔硅通孔的多个焊盘。贯通硅通孔包括供电电源电位或接地电位的电源系统的贯穿硅通孔，以及供给各种信号的信号系统的通孔硅通孔。在焊盘中，连接到电源系统的贯穿硅通孔的焊盘的至少一个尺寸大于连接到信号系统的通过硅通孔的焊盘的尺寸。因此，可以确保更大的寄生电容。

35. 发明授权

US06661092B2 Memory module 有权
标题翻译：内存模块
公开(公告)号：US06661092B2
公开(公告)日：2003-12-09
申请号：US10205040
申请日：2002-07-25
申请人： Kayoko Shibata , Yoji Nishio
发明人： Kayoko Shibata , Yoji Nishio
IPC分类号： H01L2334
CPC分类号： G11C5/147 , H01L2924/0002 , H01L2924/00
摘要： A memory module is provided with a resistor serving as an impedance adjuster which is connected directly or indirectly to an output terminal of an output transistor of a C/A register. The resistor adjusts the output impedance of the C/A register viewed from an input terminal of a C/A bus in such a manner that the output impedance becomes substantially constant within an operating voltage range of an internal signal output from the C/A register. The memory module is further provided with a capacitor serving as a rise time/fall time adjuster which adjusts rise time and fall time of the internal signal to specific values such that satisfactory waveforms are obtained.
摘要翻译：存储器模块设置有用作阻抗调节器的电阻器，其直接或间接地连接到C / A寄存器的输出晶体管的输出端子。该电阻调节从C / A总线的输入端子观察的C / A寄存器的输出阻抗，使得输出阻抗在从C / A寄存器输出的内部信号的工作电压范围内变得基本恒定。存储器模块还具有用作上升时间/下降时间调节器的电容器，其将内部信号的上升时间和下降时间调整到特定值，从而获得令人满意的波形。

36. 发明授权

US08584061B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08584061B2
公开(公告)日：2013-11-12
申请号：US12923800
申请日：2010-10-07
申请人： Kayoko Shibata , Hitoshi Miwa , Yoshihiko Inoue
发明人： Kayoko Shibata , Hitoshi Miwa , Yoshihiko Inoue
IPC分类号： G06F17/50
CPC分类号： H01L27/10897 , G11C5/063 , G11C29/025 , G11C29/12 , G11C29/1201 , H01L22/22 , H01L23/481 , H01L23/5384 , H01L25/0657 , H01L27/1052 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/01019 , H01L2924/01037 , H01L2924/01055
摘要： To include a first semiconductor chip including driver circuits, a second semiconductor chip including receiver circuits, and through silicon vias provided in the second semiconductor chip. The first semiconductor chip includes an output switching circuit that exclusively connects an output terminal of an i-th driver circuit (where i is an integer among 1 to n) to one through silicon via among an i-th through silicon via to an (i+m)-th through silicon via. The second semiconductor chip includes an input switching circuit that exclusively connects an input terminal of an i-th receiver circuit (where i is an integer among 1 to n) to one through silicon via among the i-th through silicon via to the (i+m)-th through silicon via. With this configuration, because a difference in wiring lengths does not occur between signal paths before and after replacement of through silicon vias, the signal quality can be enhanced.
摘要翻译：包括包括驱动电路的第一半导体芯片，包括接收电路的第二半导体芯片，以及设置在第二半导体芯片中的硅通孔。第一半导体芯片包括输出开关电路，其将第i个驱动器电路的输出端（其中i为1至n之间的整数）通过硅通孔中的一个通过硅通孔连接至第（i + m）通过硅通孔。第二半导体芯片包括输入开关电路，其将第i个接收器电路（其中i是1至n之间的整数）的输入端与第i个至第 + m）通过硅通孔。利用这种配置，由于在通过硅通孔的替换之前和之后的信号路径之间不发生布线长度的差异，所以可以提高信号质量。

37. 发明申请

US20110084758A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20110084758A1
公开(公告)日：2011-04-14
申请号：US12923800
申请日：2010-10-07
申请人： Kayoko Shibata , Hitoshi Miwa , Yoshihiko Inoue
发明人： Kayoko Shibata , Hitoshi Miwa , Yoshihiko Inoue
IPC分类号： H01L25/00
CPC分类号： H01L27/10897 , G11C5/063 , G11C29/025 , G11C29/12 , G11C29/1201 , H01L22/22 , H01L23/481 , H01L23/5384 , H01L25/0657 , H01L27/1052 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/01019 , H01L2924/01037 , H01L2924/01055
摘要： To include a first semiconductor chip including driver circuits, a second semiconductor chip including receiver circuits, and through silicon vias provided in the second semiconductor chip. The first semiconductor chip includes an output switching circuit that exclusively connects an output terminal of an i-th driver circuit (where i is an integer among 1 to n) to one through silicon via among an i-th through silicon via to an (i+m)-th through silicon via. The second semiconductor chip includes an input switching circuit that exclusively connects an input terminal of an i-th receiver circuit (where i is an integer among 1 to n) to one through silicon via among the i-th through silicon via to the (i+m)-th through silicon via. With this configuration, because a difference in wiring lengths does not occur between signal paths before and after replacement of through silicon vias, the signal quality can be enhanced.
摘要翻译：包括包括驱动电路的第一半导体芯片，包括接收电路的第二半导体芯片，以及设置在第二半导体芯片中的硅通孔。第一半导体芯片包括输出开关电路，其将第i个驱动器电路的输出端（其中i为1至n之间的整数）通过硅通孔中的一个通过硅通孔连接至第（i + m）通过硅通孔。第二半导体芯片包括输入开关电路，其将第i个接收器电路（其中i是1至n之间的整数）的输入端与第i个至第 + m）通过硅通孔。利用这种配置，由于在通过硅通孔更换之前和之后的信号路径之间不发生布线长度的差异，所以可以提高信号质量。

38. 发明申请

US20110084404A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20110084404A1
公开(公告)日：2011-04-14
申请号：US12923787
申请日：2010-10-07
申请人： Hideyuki Yoko , Kayoko Shibata
发明人： Hideyuki Yoko , Kayoko Shibata
IPC分类号： H01L27/118
CPC分类号： H01L27/10897 , G11C5/04 , G11C5/063 , G11C29/12 , H01L22/22 , H01L23/481 , H01L25/0657 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596
摘要： One interface chip and a plurality of core chips are stacked, and these semiconductor chips are electrically connected to each other via a plurality of through silicon vias. A data signal output from a driver circuit is input into the core chip via one of the through silicon vias. An output selection circuit selects any one of the through silicon vias by activating a corresponding one of a plurality of tri-state inverters. When an inverter is activated, a primary selection circuit causes a test signal to be supplied to a receiver circuit from a test pad. When the inverter is inactivated, a data signal from any one of the through silicon vias is supplied to the receiver circuit.
摘要翻译：一个接口芯片和多个芯片堆叠，并且这些半导体芯片通过多个通孔硅电极彼此电连接。从驱动电路输出的数据信号通过硅通孔之一输入到芯片芯片。输出选择电路通过激活多个三态反相器中的相应一个来选择贯穿硅通孔中的任何一个。当反相器被激活时，主选择电路使测试信号从测试垫提供给接收器电路。当逆变器失活时，来自任何一个通孔的数据信号被提供给接收器电路。

39. 发明授权

US07161820B2 Memory module and memory system having an expandable signal transmission, increased signal transmission and/or high capacity memory 有权
标题翻译：具有可扩展信号传输，增加的信号传输和/或高容量存储器的存储器模块和存储器系统
公开(公告)号：US07161820B2
公开(公告)日：2007-01-09
申请号：US10628517
申请日：2003-07-28
申请人： Seiji Funaba , Yoji Nishio , Kayoko Shibata
发明人： Seiji Funaba , Yoji Nishio , Kayoko Shibata
IPC分类号： G11C5/00 , G11C5/06
CPC分类号： G11C5/04 , G11C5/063 , G11C7/1048 , G11C11/4093 , G11C2207/105 , H01L2224/16225 , H01L2924/15192 , H01L2924/15311 , H01L2924/19107
摘要： A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.
摘要翻译：存储器模块具有在板的前表面和后表面上共享总线的多个DRAM（115）。总线通过通孔（113）从端子（111）连接到带状线（112）的一端，并且带状线的另一端通过通孔（113）连接到另一层中的带状线孔（119）用于使线路循环。设置在终端电压端子（VTT）附近的终端电阻器（120）通过通孔连接到另一层中的环形带状线。 DRAM端子通过通孔连接到带状线。该存储器模块通过连接器安装在其上提供存储器控制器的母板上。母线的有效特性阻抗与母板线路特性阻抗匹配。

40. 发明授权

US08847221B2 Stacked semiconductor device and method of testing the same 有权
标题翻译：堆叠半导体器件及其测试方法
公开(公告)号：US08847221B2
公开(公告)日：2014-09-30
申请号：US11870550
申请日：2007-10-11
申请人： Kayoko Shibata
发明人： Kayoko Shibata
IPC分类号： H01L23/58 , G01R31/3185 , G11C29/02 , H01L21/66 , H01L23/48 , G11C29/50
CPC分类号： G01R31/318513 , G11C29/02 , G11C29/022 , G11C29/025 , G11C2029/5006 , H01L22/32 , H01L23/481 , H01L2224/0401 , H01L2224/05554 , H01L2224/16145 , H01L2924/13091 , H01L2924/3011 , H01L2924/00
摘要： A stacked semiconductor device includes: an internal circuit; a through electrode provided to penetrate through a semiconductor substrate; a test wiring to which a predetermined potential different from a substrate potential is supplied at a time of a test; a first switch arranged between the through electrode and the internal circuit; a second switch arranged between the through electrode and the test wiring; and a control circuit that exclusively turns on the first and the second switches. Thereby, it becomes possible to perform an insulation test in a state that the through electrode and the internal circuit are cut off. Thus, even when a slight short-circuit that does not lead to a current defect occurs, the short circuit can be detected.
摘要翻译：叠层半导体器件包括：内部电路; 设置成贯通半导体基板的贯通电极; 在测试时提供与基板电位不同的预定电位的测试布线; 布置在所述通孔电极和所述内部电路之间的第一开关; 布置在所述通孔电极和所述测试布线之间的第二开关; 以及专门打开第一和第二开关的控制电路。由此，可以在切断贯通电极和内部电路的状态下进行绝缘试验。因此，即使发生不会导致电流缺陷的轻微短路，也可以检测短路。

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