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31. 发明申请

US20050051831A1 Nonvolatile semiconductor memory and method for fabricating the same 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20050051831A1
公开(公告)日：2005-03-10
申请号：US10890132
申请日：2004-07-14
申请人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
发明人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/76 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/76838 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first interconnect extended in a row direction; a second interlayer insulator formed on the lower conductive plug and the first interlayer insulator film; an upper conductive plug; and a second interconnect formed on the second interlayer insulator contacting with the top of the upper conductive plug extended in the column direction.
摘要翻译：非易失性半导体存储器包括：第一半导体层; 形成在第一半导体层上的第二半导体区域，具有沿列方向延伸的器件隔离区域; 形成在所述第一半导体层上方的第一层间绝缘膜; 连接到第二半导体区域的下导电插塞; 沿行方向延伸的第一互连; 形成在下导电插塞和第一层间绝缘膜上的第二层间绝缘膜; 上导电插头; 以及形成在与沿列方向延伸的上导电插塞的顶部接触的第二层间绝缘体上的第二互连。

32. 发明申请

US20050006696A1 Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US20050006696A1
公开(公告)日：2005-01-13
申请号：US10850408
申请日：2004-05-21
申请人： Mitsuhiro Noguchi , Akira Goda , Masayuki Tanaka
发明人： Mitsuhiro Noguchi , Akira Goda , Masayuki Tanaka
IPC分类号： G11C16/04 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L27/148 , H01L29/51 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , G11C16/0466 , G11C16/0483 , H01L27/115 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/792
摘要： A semiconductor memory having an electrically writable/erasable memory cell includes a first gate insulating layer made from a compound containing silicon and oxygen; a first charge-storage layer being in contact with the first gate insulating layer made from a silicon nitride film, a silicon oxynitride film, or an alumina film; a second insulating layer thicker than the first gate insulting layer; a second charge-storage layer being in contact with the second insulating layer; a third insulating layer thicker than the first gate insulating layer being in contact with the second charge-storage layer; and a control electrode upon the third insulating layer.
摘要翻译：具有电可写/可擦除存储单元的半导体存储器包括由含硅和氧的化合物制成的第一栅极绝缘层; 与由氮化硅膜，氮氧化硅膜或氧化铝膜构成的第一栅极绝缘层接触的第一电荷存储层; 比第一栅极绝缘层厚的第二绝缘层; 与第二绝缘层接触的第二电荷存储层; 比所述第一栅极绝缘层更厚的与所述第二电荷存储层接触的第三绝缘层; 以及在所述第三绝缘层上的控制电极。

33. 发明申请

US20100052032A1 Nonvolatile semiconductor memory and method for fabricating the same 有权
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20100052032A1
公开(公告)日：2010-03-04
申请号：US12588203
申请日：2009-10-07
申请人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
发明人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , H01L21/76838 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first interconnect extended in a row direction; a second interlayer insulator formed on the lower conductive plug and the first interlayer insulator film; an upper conductive plug; and a second interconnect formed on the second interlayer insulator contacting with the top of the upper conductive plug extended in the column direction.
摘要翻译：非易失性半导体存储器包括：第一半导体层; 形成在第一半导体层上的第二半导体区域，具有沿列方向延伸的器件隔离区域; 形成在所述第一半导体层上方的第一层间绝缘膜; 连接到第二半导体区域的下导电插塞; 沿行方向延伸的第一互连; 形成在下导电插塞和第一层间绝缘膜上的第二层间绝缘膜; 上导电插头; 以及形成在与沿列方向延伸的上导电插塞的顶部接触的第二层间绝缘体上的第二互连。

34. 发明授权

US07622762B2 Nonvolatile semiconductor memory and method for fabricating the same 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US07622762B2
公开(公告)日：2009-11-24
申请号：US12000396
申请日：2007-12-12
申请人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
发明人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , H01L21/76838 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first interconnect extended in a row direction; a second interlayer insulator formed on the lower conductive plug and the first interlayer insulator film; an upper conductive plug; and a second interconnect formed on the second interlayer insulator contacting with the top of the upper conductive plug extended in the column direction.
摘要翻译：非易失性半导体存储器包括：第一半导体层; 形成在第一半导体层上的第二半导体区域，具有沿列方向延伸的器件隔离区域; 形成在所述第一半导体层上方的第一层间绝缘膜; 连接到第二半导体区域的下导电插塞; 沿行方向延伸的第一互连; 形成在下导电插塞和第一层间绝缘膜上的第二层间绝缘膜; 上导电插头; 以及形成在与沿列方向延伸的上导电插塞的顶部接触的第二层间绝缘体上的第二互连。

35. 发明授权

US07099190B2 Data storage system 失效
标题翻译：数据存储系统
公开(公告)号：US07099190B2
公开(公告)日：2006-08-29
申请号：US10822177
申请日：2004-04-12
申请人： Mitsuhiro Noguchi , Akira Goda
发明人： Mitsuhiro Noguchi , Akira Goda
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G06F11/1008 , G11C16/0483
摘要： A data storage system, which includes a plurality of pages, each of which includes a plurality of first memory cells, from which at least binary data can be read-out a plurality of times without destruction; a circuit which receives data-output of at least one first page, detects an error in at least one bit of data, and outputs information of the error position; another circuit which determines whether data of an error bit is “1” or “0”. When the determination is “1” or “0”, the first memory cell of the first page is erased, and error-corrected data is written.
摘要翻译：一种数据存储系统，其包括多个页面，每个页面包括多个第一存储器单元，至少二进制数据可从多个第一存储单元读出多次而不被破坏; 接收至少一个第一页的数据输出的电路检测至少一位数据中的错误，并输出错误位置的信息; 确定错误位的数据是“1”还是“0”的另一个电路。当确定为“1”或“0”时，第一页的第一存储单元被擦除，并且写入纠错数据。

36. 发明授权

US07026241B2 Superconductor device and method of manufacturing the same 失效
公开(公告)号：US07026241B2
公开(公告)日：2006-04-11
申请号：US10943250
申请日：2004-09-17
申请人： Akira Goda , Mitsuhiro Noguchi , Yuji Takeuchi , Hiroaki Hazama
发明人： Akira Goda , Mitsuhiro Noguchi , Yuji Takeuchi , Hiroaki Hazama
IPC分类号： H01L21/4763
CPC分类号： H01L27/11568 , H01L21/76838 , H01L23/485 , H01L23/522 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11531 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprising element regions formed in a semiconductor substrate, conductor plugs embedded in an interlayer insulation film, and wiring layers connected to the plugs, wherein the plugs are arranged on a straight line orthogonal to a longitudinal direction of the wiring layer in the same pitch as the wiring layers such that the straight line and upper surfaces of the plugs are superposed each other, and when the plugs are viewed in a cross section parallel to a main surface of the substrate and a distance which is between those two edge points of each of the plugs where a split line which passes through a center of each of the plugs passes is defined as a contact diameter, the contact diameter has three or more maximum values and three or more minimum values while the split line is rotated in the cross section by 360 degrees.

37. 发明申请

US20050237847A1 Semiconductor device with source line and fabrication method thereof 审中-公开
公开(公告)号：US20050237847A1
公开(公告)日：2005-10-27
申请号：US11171300
申请日：2005-07-01
申请人： Akira Goda , Mitsuhiro Noguchi
发明人： Akira Goda , Mitsuhiro Noguchi
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C8/00
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： A semiconductor device comprises a plurality of field-effect transistors and a common source line. Each of the plurality of memory cell transistors includes a semiconductor region of a first conductivity type formed in a semiconductor substrate, a source region and a drain region of a second conductivity type formed in the semiconductor region, an information storage portion capable of electrically writing and erasing data, and at least one control gate electrode including a conductive layer. The common source line is formed on the semiconductor region of the first conductivity type, and electrically connects the source regions of the memory cell transistors. The common source line includes a conductive layer that has a film thickness substantially equal to a film thickness of the conductive layer included in the control gate electrode and is formed of the same material as that of the conductive layer included in the control gate electrode.

38. 发明授权

US06917072B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06917072B2
公开(公告)日：2005-07-12
申请号：US10393946
申请日：2003-03-24
申请人： Mitsuhiro Noguchi , Akira Goda
发明人： Mitsuhiro Noguchi , Akira Goda
IPC分类号： H01L21/8247 , H01L21/8246 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11573 , H01L29/792
摘要： A semiconductor memory device comprises a first conductivity type semiconductor region, a second conductivity type source and drain regions provided in the semiconductor region, a gate insulating film structure provided on the semiconductor region between the source region and drain region and including a first insulating film, a charge accumulation layer and a second insulating film, the charge accumulation layer being selected from a silicon nitride film, a silicon oxynitride film, an alumina film and a stacked film of these films, a control gate electrode provided on the second insulating film, a gate sidewall provided on a side of the control gate electrode and having a thickness thinner than that of the second insulating film in the center of the control gate electrode, a third insulating film provided above the control gate electrode, and a fourth insulating film provided to cover the gate electrode sidewall and the third insulating film.
摘要翻译：半导体存储器件包括第一导电型半导体区域，设置在半导体区域中的第二导电类型源极和漏极区域，设置在源极区域和漏极区域之间的半导体区域上并且包括第一绝缘膜的栅极绝缘膜结构，电荷累积层和第二绝缘膜，所述电荷累积层选自氮化硅膜，氮氧化硅膜，氧化铝膜和这些膜的堆叠膜，设置在第二绝缘膜上的控制栅电极，设置在所述控制栅电极的一侧上并且具有比所述控制栅极电极中心的所述第二绝缘膜的厚度薄的栅极侧壁，设置在所述控制栅极电极上方的第三绝缘膜，以及设置到覆盖栅电极侧壁和第三绝缘膜。

39. 发明授权

US06894931B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US06894931B2
公开(公告)日：2005-05-17
申请号：US10393453
申请日：2003-03-21
申请人： Toshitake Yaegashi , Akira Goda , Mitsuhiro Noguchi
发明人： Toshitake Yaegashi , Akira Goda , Mitsuhiro Noguchi
IPC分类号： G11C16/00 , G11C16/04 , G11C16/34 , G11C16/06
CPC分类号： G11C16/0466 , G11C16/3468
摘要： A cell array is configured by arranging a plurality of electrically writable erasable nonvolatile memory cells on a semiconductor substrate. Each of the memory cells has a charge accumulation layer formed via a first gate insulating film and a gate electrode formed on the charge accumulation layer via a second gate insulating film. A control circuit controls the sequence of writing and erasing the data into and from a memory cell selected in the memory cell. In writing the data into the memory cell, a first write operation is to apply a write pulse voltage with a first step-up voltage between the gate electrode and the semiconductor substrate. A second write operation is to apply a write pulse voltage with a second step-up voltage lower than the first step-up voltage.
摘要翻译：通过在半导体衬底上布置多个电可写入的可擦除非易失性存储单元来配置单元阵列。每个存储单元具有通过第一栅极绝缘膜和通过第二栅极绝缘膜在电荷累积层上形成的栅电极形成的电荷累积层。控制电路控制将数据写入和擦除存储单元中选择的存储单元的顺序。在将数据写入存储单元中，第一写入操作是在栅电极和半导体衬底之间施加具有第一升压电压的写入脉冲电压。第二写入操作是施加具有低于第一升压电压的第二升压电压的写入脉冲电压。

40. 发明申请

US20050037612A1 Superconductor device and method of manufacturing the same 失效
标题翻译：超导体装置及其制造方法
公开(公告)号：US20050037612A1
公开(公告)日：2005-02-17
申请号：US10943250
申请日：2004-09-17
申请人： Akira Goda , Mitsuhiro Noguchi , Yuji Takeuchi , Hiroaki Hazama
发明人： Akira Goda , Mitsuhiro Noguchi , Yuji Takeuchi , Hiroaki Hazama
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8246 , H01L21/8247 , H01L23/485 , H01L23/522 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/788 , H01L29/792 , H01L21/4763 , H01L21/44
CPC分类号： H01L27/11568 , H01L21/76838 , H01L23/485 , H01L23/522 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11531 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprising element regions formed in a semiconductor substrate, conductor plugs embedded in an interlayer insulation film, and wiring layers connected to the plugs, wherein the plugs are arranged on a straight line orthogonal to a longitudinal direction of the wiring layer in the same pitch as the wiring layers such that the straight line and upper surfaces of the plugs are superposed each other, and when the plugs are viewed in a cross section parallel to a main surface of the substrate and a distance which is between those two edge points of each of the plugs where a split line which passes through a center of each of the plugs passes is defined as a contact diameter, the contact diameter has three or more maximum values and three or more minimum values while the split line is rotated in the cross section by 360 degrees.
摘要翻译：一种半导体器件，包括形成在半导体衬底中的元件区域，嵌入在层间绝缘膜中的导体插塞和连接到插头的布线层，其中插头布置在与其中的布线层的纵向正交的直线上作为布线层的间距，使得插塞的直线和上表面彼此重叠，并且当在与基板的主表面平行的横截面中观察插塞时，并且在两个边缘点之间的距离通过每个塞子的中心的分割线通过的每个插头被定义为接触直径，接触直径具有三个或更多个最大值和三个或更多个最小值，同时分叉线在十字形中旋转截面360度。

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