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31. 发明申请

US20110318189A1 CROSSFLOW FAN AND AIR CONDITIONER PROVIDED WITH SAME 有权
标题翻译：交叉风扇和空气调节器
公开(公告)号：US20110318189A1
公开(公告)日：2011-12-29
申请号：US13255196
申请日：2010-03-09
申请人： Hironobu Teraoka , Shimei Tei , Toru Iwata
发明人： Hironobu Teraoka , Shimei Tei , Toru Iwata
IPC分类号： F01D5/14
CPC分类号： F04D29/283 , F04D17/04 , F04D29/30 , F04D29/681 , F24F1/0025 , F24F2001/0048
摘要： A crossflow fan includes a rotary impeller formed by curved blades 42. Each of the blades 42 has an outer peripheral edge 43 close to the centrifugal side of the impeller and an inner peripheral edge 44 close to the rotation axis side of the impeller. A plurality of cutouts 45 are formed in the outer peripheral edge 43 and spaced apart at predetermined intervals. Dimples 48 for changing a boundary layer from a laminar flow to a turbulent flow are formed in a negative pressure surface 4q of each blade 42 in the vicinity of the outer peripheral edge 43 to prevent the gas flowing around the blade 42 from separating from the blade 42.
摘要翻译：横流风扇包括由弯曲叶片42形成的旋转叶轮。每个叶片42具有靠近叶轮的离心侧的外周边缘43和靠近叶轮的旋转轴线侧的内周边缘44。多个切口45形成在外周边缘43中并且以预定间隔隔开。在每个叶片42的外周边缘43附近的负压表面4q中形成用于将边界层从层流改变为湍流的凹坑48，以防止在叶片42周围流动的气体与叶片分离 42。

32. 发明授权

US08004433B2 Semiconductor integrated circuit and transmitter apparatus having the same 有权
标题翻译：具有相同的半导体集成电路和发射机装置
公开(公告)号：US08004433B2
公开(公告)日：2011-08-23
申请号：US12376405
申请日：2007-07-31
申请人： Manabu Kawabata , Ryogo Yanagisawa , Toru Iwata , Hirokazu Sugimoto
发明人： Manabu Kawabata , Ryogo Yanagisawa , Toru Iwata , Hirokazu Sugimoto
IPC分类号： H03M9/00
CPC分类号： H03K5/135 , H03L7/18 , H03M9/00 , H04L7/0008
摘要： A semiconductor integrated circuit (10D) for receiving a parallel data signal and a first clock signal and outputting a serial data signal and a second clock signal, wherein a first clock generation circuit (15) produces a third clock signal obtained by multiplying the first clock signal by X/Y. A second clock generation circuit (11) has a variable transmission characteristic, and produces a fourth clock signal obtained by multiplying the third clock signal by N. A parallel/serial conversion section (12) converts the parallel data signal, which has been converted by a scaler (16), to the serial data signal in synchronism with the fourth clock signal. A frequency divider (13) produces a fifth clock signal obtained by dividing a frequency of the fourth clock signal by N. A selector (14) selectively outputs, as the second clock signal, one of the third and fifth clock signals.
摘要翻译：一种用于接收并行数据信号和第一时钟信号并输出串行数据信号和第二时钟信号的半导体集成电路（10D），其中第一时钟产生电路（15）产生通过将第一时钟信号X / Y。第二时钟发生电路（11）具有可变的传输特性，并且产生通过将第三时钟信号乘以N而获得的第四时钟信号。并行/串行转换部分（12）将已被转换的并行数据信号缩放器（16），与第四时钟信号同步地连接到串行数据信号。分频器（13）产生通过将第四时钟信号的频率除以N而获得的第五时钟信号。选择器（14）有选择地输出第三和第五时钟信号之一作为第二时钟信号。

33. 发明申请

US20110164693A1 INTERFACE CIRCUIT 审中-公开
标题翻译：接口电路
公开(公告)号：US20110164693A1
公开(公告)日：2011-07-07
申请号：US13047337
申请日：2011-03-14
申请人： Yoshihide KOMATSU , Tsuyoshi Ebuchi , Yukio Arima , Toru Iwata
发明人： Yoshihide KOMATSU , Tsuyoshi Ebuchi , Yukio Arima , Toru Iwata
IPC分类号： H04L27/00
CPC分类号： H04L7/0008 , G06F1/12 , H04L5/1469 , H04L5/16 , H04L25/0272 , H04L25/0298
摘要： An interface circuit including an LSI (10) in a host device (1), and an LSI (20) in a sub device (2), respectively. The LSI (10) generates a first transmission clock signal (TC1) and a first reception clock signal (RC1) separately in accordance with a first reference clock signal (RFC1). The LSI (10) also generates a second reference clock signal (RFC2) for a sub device (2). The reference clock signal (RFC2) is converted into a differential clock signal, and then transmitted to the sub device (2). An LSI (20) of the sub device (2) generates a second transmission clock signal (TC2) and a second reception clock signal (RC2) separately in accordance with a third reference clock signal (RFC3) converted from the differential clock signal.
摘要翻译：一种在主机（1）中包括LSI（10）的接口电路和分装置（2）中的LSI（20）。 LSI（10）根据第一参考时钟信号（RFC1）分别产生第一传输时钟信号（TC1）和第一接收时钟信号（RC1）。 LSI（10）还为子设备（2）生成第二参考时钟信号（RFC2）。参考时钟信号（RFC2）被转换为差分时钟信号，然后发送到子设备（2）。子装置（2）的LSI（20）根据从差分时钟信号转换的第三参考时钟信号（RFC3）分别产生第二传输时钟信号（TC2）和第二接收时钟信号（RC2）。

34. 发明授权

US07957498B2 Data receiver device and data transmission/reception system 有权
标题翻译：数据接收设备和数据发送/接收系统
公开(公告)号：US07957498B2
公开(公告)日：2011-06-07
申请号：US11995423
申请日：2006-07-10
申请人： Hirokazu Sugimoto , Toru Iwata
发明人： Hirokazu Sugimoto , Toru Iwata
IPC分类号： H04L7/00
CPC分类号： H04L7/0004 , H04L25/14
摘要： The data receiver device includes: a bit phase synchronizing circuit (10) for performing phase adjustment of a received data signal to set a predetermined phase relationship between the data signal and a corresponding clock signal; and a state detection circuit (20) for outputting a detection signal once detecting that the data signal inputted into the bit phase synchronizing circuit (10) is in a stable state based on a data signal phase-adjusted by the bit phase synchronizing circuit (10) and a corresponding clock signal. The bit phase synchronizing circuit (10) initializes the phase adjustment of the data signal when receiving the detection signal.
摘要翻译：数据接收装置包括：位相位同步电路（10），用于执行接收数据信号的相位调整，以设置数据信号与对应的时钟信号之间的预定相位关系; 一旦检测到输入到位相位同步电路（10）的数据信号基于由位相位同步电路（10）相位调整的数据信号而处于稳定状态，则输出检测信号的状态检测电路（20））和相应的时钟信号。位相位同步电路（10）在接收到检测信号时初始化数据信号的相位调整。

35. 发明授权

US07864252B2 Video signal processor capable of suppressing excessive heat generation, method using the same, display device and method using the same 有权
标题翻译：能够抑制过度发热的视频信号处理器，使用其的方法，显示装置及使用其的方法
公开(公告)号：US07864252B2
公开(公告)日：2011-01-04
申请号：US11071190
申请日：2005-03-04
申请人： Satoshi Takahashi , Ryogo Yanagisawa , Toru Iwata
发明人： Satoshi Takahashi , Ryogo Yanagisawa , Toru Iwata
IPC分类号： H04N5/63 , H04N17/00 , H04N5/44 , H03L7/00
CPC分类号： G09G5/006 , G09G3/2092
摘要： A video signal processor for processing input video data in accordance with an input clock signal includes: an input section for changing the format of the video data and outputting resultant data; a logic section for decoding the data output from the input section and outputting decoded data; and a frequency detector for detecting that the clock signal has a frequency higher than a given frequency and outputting a result of the detection as a detection signal. When the frequency of the clock signal is higher than the given frequency, operation of at least part of circuits constituting the video signal processor is stopped in accordance with the detection signal.
摘要翻译：用于根据输入时钟信号处理输入视频数据的视频信号处理器包括：输入部分，用于改变视频数据的格式并输出结果数据; 逻辑部分，用于对从输入部分输出的数据进行解码并输出解码数据; 以及频率检测器，用于检测时钟信号具有高于给定频率的频率，并将检测结果作为检测信号输出。当时钟信号的频率高于给定频率时，根据检测信号停止构成视频信号处理器的电路的至少一部分的操作。

36. 发明授权

US07843224B2 Interface circuit that can switch between single-ended transmission and differential transmission 有权
标题翻译：接口电路可以在单端传输和差分传输之间切换
公开(公告)号：US07843224B2
公开(公告)日：2010-11-30
申请号：US12262613
申请日：2008-10-31
申请人： Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito , Toru Iwata , Masayuki Toyama , Kyoko Hirata
发明人： Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito , Toru Iwata , Masayuki Toyama , Kyoko Hirata
IPC分类号： H03K19/094
CPC分类号： H04L25/028 , H04L25/0272
摘要： An object of the present invention is to realize reduction in an area of an output stage driver in an interface circuit that switches between two transmission systems. The interface circuit has two driver circuits and a drive control circuit that can switch between two driving systems that are a voltage driving system and a current driving system. The two driver circuits are connected to a power supply potential via the drive control circuit. Two input signals and inverted logic signals of the input signals are inputted via a selection circuit. According to a control signal inputted into the drive control circuit, the interface circuit switches between the voltage-driving type single-ended transmission system and current driving type differential transmission system.
摘要翻译：本发明的目的是实现在两个传输系统之间切换的接口电路中的输出级驱动器的面积的减小。接口电路具有两个驱动电路和驱动控制电路，该电路可以在作为电压驱动系统和电流驱动系统的两个驱动系统之间切换。两个驱动电路通过驱动控制电路连接到电源电位。通过选择电路输入输入信号的两个输入信号和反相逻辑信号。根据输入到驱动控制电路的控制信号，接口电路在电压驱动型单端传输系统和电流驱动型差动传输系统之间切换。

37. 发明申请

US20090108872A1 INTERFACE CIRCUIT THAT CAN SWITCH BETWEEN SINGLE-ENDED TRANSMISSION AND DIFFERENTIAL TRANSMISSION 有权
标题翻译：可以在单端传输和差分传输之间切换的接口电路
公开(公告)号：US20090108872A1
公开(公告)日：2009-04-30
申请号：US12262613
申请日：2008-10-31
申请人： Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito , Toru Iwata , Masayuki Toyama , Kyoko Hirata
发明人： Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito , Toru Iwata , Masayuki Toyama , Kyoko Hirata
IPC分类号： H03K19/0175
CPC分类号： H04L25/028 , H04L25/0272
摘要： An object of the present invention is to realize reduction in an area of an output stage driver in an interface circuit that switches between two transmission systems. The interface circuit has two driver circuits and a drive control circuit that can switch between two driving systems that are a voltage driving system and a current driving system. The two driver circuits are connected to a power supply potential via the drive control circuit. Two input signals and inverted logic signals of the input signals are inputted via a selection circuit. According to a control signal inputted into the drive control circuit, the interface circuit switches between the voltage-driving type single-ended transmission system and current driving type differential transmission system.
摘要翻译：本发明的目的是实现在两个传输系统之间切换的接口电路中的输出级驱动器的面积的减小。接口电路具有两个驱动电路和驱动控制电路，该电路可以在作为电压驱动系统和电流驱动系统的两个驱动系统之间切换。两个驱动电路通过驱动控制电路连接到电源电位。通过选择电路输入输入信号的两个输入信号和反相逻辑信号。根据输入到驱动控制电路的控制信号，接口电路在电压驱动型单端传输系统和电流驱动型差动传输系统之间切换。

38. 发明申请

US20090086852A1 DATA RECEIVER DEVICE AND DATA TRANSMISSION/RECEPTION SYSTEM 有权
标题翻译：数据接收设备和数据传输/接收系统
公开(公告)号：US20090086852A1
公开(公告)日：2009-04-02
申请号：US11995423
申请日：2006-07-10
申请人： Hirokazu Sugimoto , Toru Iwata
发明人： Hirokazu Sugimoto , Toru Iwata
IPC分类号： H04L7/06
CPC分类号： H04L7/0004 , H04L25/14
摘要： The data receiver device includes: a bit phase synchronizing circuit (10) for performing phase adjustment of a received data signal to set a predetermined phase relationship between the data signal and a corresponding clock signal; and a state detection circuit (20) for outputting a detection signal once detecting that the data signal inputted into the bit phase synchronizing circuit (10) is in a stable state based on a data signal phase-adjusted by the bit phase synchronizing circuit (10) and a corresponding clock signal. The bit phase synchronizing circuit (10) initializes the phase adjustment of the data signal when receiving the detection signal.
摘要翻译：数据接收装置包括：位相位同步电路（10），用于执行接收数据信号的相位调整，以设置数据信号与对应的时钟信号之间的预定相位关系; 一旦检测到输入到位相位同步电路（10）的数据信号基于由位相位同步电路（10）相位调整的数据信号而处于稳定状态，则输出检测信号的状态检测电路（20））和相应的时钟信号。位相位同步电路（10）在接收到检测信号时初始化数据信号的相位调整。

39. 发明申请

US20070183175A1 Charge pumping circuit 有权
标题翻译：充电泵电路
公开(公告)号：US20070183175A1
公开(公告)日：2007-08-09
申请号：US11637687
申请日：2006-12-13
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata
IPC分类号： H02M7/00
CPC分类号： H02M3/07 , H03L7/0895 , H03L7/0896
摘要： A charge pumping circuit includes a first switch for controlling one of push and pull operations in accordance with a first control signal; a current mirror circuit constructed from transistors each having a different polarity from the first switch; a second switch for controlling current input to the current mirror circuit in accordance with a second control signal, the second switch being constructed from a transistor having the same characteristic as a transistor used for constructing the first switch; a first MOS capacitor one end of which is connected to an input side of the current mirror circuit; a second MOS capacitor receiving, at one end thereof, a current concerned with the push and pull operations; and a voltage buffer connected to the first and second MOS capacitors. The other of the push and pull operations is performed with an output current of the current mirror circuit.
摘要翻译：电荷泵浦电路包括：第一开关，用于根据第一控制信号控制推挽操作中的一个; 由与所述第一开关具有不同极性的晶体管构成的电流镜电路; 第二开关，用于根据第二控制信号控制到电流镜电路的电流输入，第二开关由具有与用于构造第一开关的晶体管相同的特性的晶体管构成; 第一MOS电容器，其一端连接到电流镜电路的输入侧; 在其一端接收与推挽操作有关的电流的第二MOS电容器; 以及连接到第一和第二MOS电容器的电压缓冲器。推挽操作中的另一个用电流镜电路的输出电流进行。

40. 发明授权

US07030688B2 Low-pass filter for a PLL, phase-locked loop and semiconductor integrated circuit 失效
标题翻译：用于PLL，锁相环和半导体集成电路的低通滤波器
公开(公告)号：US07030688B2
公开(公告)日：2006-04-18
申请号：US10500875
申请日：2003-05-22
申请人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara , Masahiro Fukui , Takefumi Yoshikawa , Toru Iwata , Shiro Sakiyama , Ryoichi Suzuki
发明人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara , Masahiro Fukui , Takefumi Yoshikawa , Toru Iwata , Shiro Sakiyama , Ryoichi Suzuki
IPC分类号： H03K5/00
CPC分类号： H03L7/0812 , H03L7/0891 , H03L7/0893 , H03L7/0896 , H03L7/093
摘要： The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means (31) for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element (311) included in the first filtering means (31) for allowing a first current to flow in accordance with the first voltage; current generating means (32) for generating a second current at a given rate to the first current; second filtering means (33) for accepting, as an input, the second current and outputting a second voltage; and adding means (34) for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.
摘要翻译：本发明提供一种适合用作PLL或DLL的环路滤波器的低通滤波器，其具有与常规滤波特性相同的滤波特性，并且可以在较小的电路面积中实现。低通滤波器包括第一滤波装置（31），用于接收输入到低通滤波器的输入信号作为输入，并输出第一电压; 包括在第一过滤装置（31）中的用于允许第一电流根据第一电压流动的电路元件（311）电流产生装置（32），用于以给定的速率产生与第一电流的第二电流; 第二滤波装置（33），用于接受第二电流作为输入并输出第二电压; 以及添加装置（34），用于将第一电压和第二电压相加，并输出低通滤波器的输出信号，其中第二电流被设置为小于第一电流。

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