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31. 发明授权

US5625213A Top floating-gate flash EEPROM structure 失效
标题翻译：顶部浮栅闪存EEPROM结构
公开(公告)号：US5625213A
公开(公告)日：1997-04-29
申请号：US500104
申请日：1995-07-10
申请人： Gary Hong , Chen-Chiu Hsue
发明人： Gary Hong , Chen-Chiu Hsue
IPC分类号： H01L21/336 , H01L21/8247 , H01L29/788
CPC分类号： H01L29/66825 , H01L27/11517
摘要： A method for forming, and a resultant structure of, a top floating gate FLASH EEPROM cell are described. There is a first insulating structure over a silicon substrate, whereby the first insulating structure is a gate oxide. A first conductive structure is formed over the first insulating structure, whereby the first conductive structure is a control gate. There is a first insulating layer over the surfaces of the first conductive structure, whereby the first insulating layer is an interpoly dielectric. There is a second conductive structure formed over the first insulating layer and over a portion of the silicon substrate adjacent to the first insulating structure, whereby the second conductive structure is a floating gate. A second insulating layer is formed between the silicon substrate and the second conductive structure, whereby the second insulating layer is a tunnel oxide. Active regions in the silicon substrate, implanted with a conductivity-imparting dopant, are formed under the second insulating layer but are horizontally a distance from the first insulating structure.
摘要翻译：描述了用于形成顶部浮置栅极FLASH EEPROM单元的方法和结果。在硅衬底上存在第一绝缘结构，由此第一绝缘结构是栅极氧化物。在第一绝缘结构上形成第一导电结构，由此第一导电结构是控制栅极。在第一导电结构的表面上存在第一绝缘层，由此第一绝缘层是互聚电介质。在第一绝缘层上形成第二导电结构，并且在与硅衬底相邻的第一绝缘结构的一部分之上形成第二导电结构，由此第二导电结构是浮栅。在硅衬底和第二导电结构之间形成第二绝缘层，由此第二绝缘层是隧道氧化物。在第二绝缘层的下方形成硅衬底中注入导电性赋予剂的有源区，但与水平方向距离第一绝缘结构。

32. 发明授权

US5616946A VLSI ROM programmed by selective diode formation 失效
标题翻译：通过选择性二极管形成编程的VLSI ROM
公开(公告)号：US5616946A
公开(公告)日：1997-04-01
申请号：US597542
申请日：1996-04-25
申请人： Chen-Chung Hsu , Gary Hong
发明人： Chen-Chung Hsu , Gary Hong
IPC分类号： H01L21/8229 , H01L27/102 , H01L27/112
CPC分类号： H01L21/8229 , H01L27/1021 , Y10S257/91 , Y10S438/981
摘要： A method for fabricating read only memory, (ROM), devices, has been developed. The programmable cell of this ROM device is comprised of a P/N diode, place in a N+ buried bit line. The diode formation is accomplished using outdiffusion from a P+ polysilicon wordline, that is in direct contact to a specific bit line region.
摘要翻译：已经开发了用于制造只读存储器（ROM），器件的方法。该ROM器件的可编程单元由P / N二极管组成，位于N +掩埋位线中。二极管形成是通过使用来自P +多晶硅字线的外扩散实现的，其与特定位线区域直接接触。

33. 发明授权

US5576232A Fabrication process for flash memory in which channel lengths are controlled 失效
标题翻译：控制通道长度的闪存的制作过程
公开(公告)号：US5576232A
公开(公告)日：1996-11-19
申请号：US353673
申请日：1994-12-12
申请人： Gary Hong
发明人： Gary Hong
IPC分类号： H01L21/8247
CPC分类号： H01L27/11517
摘要： A process for fabricating memory cells for split-gate flash memory devices is disclosed to feature self-alignment and therefore precisely defined channel lengths for the floating-gate and isolation transistors of the memory cell. A gate oxide layer, a first conducting layer, and a gate dielectric layer are formed in sequence on a semiconductor substrate. A conducting strip is formed on the gate dielectric layer. The conducting strip is covered with a shielding layer. The gate dielectric layer, the first conducting layer and the gate oxide layer are etched utilizing the shielding layer as a shielding mask to form a control gate for the memory cell. Thermal oxidation is applied to the entire substrate utilizing the shielding layer as a shielding mask to form a tunnel oxide layer on the surface of the substrate and isolating oxide layers on the sidewalls of the control gate. The shielding layer is removed. Electrically conducting sidewall spacers are formed on both of the sidewalls of the conducting strip. Each of the conducting sidewall spacers cover a portion of the tunnel oxide layer and are also electrically isolated from the control gate by the isolating oxide layer, forming the floating gate for the memory cell. Impurities are implanted utilizing the conducting strip and the conducting sidewall spacers as shielding masks to form source and drain regions on the substrate for the memory cell.
摘要翻译：公开了用于制造用于分离栅极闪存器件的存储器单元的工艺，其特征在于自对准，因此具有针对存储器单元的浮置栅极和隔离晶体管的精确限定的沟道长度。在半导体衬底上依次形成栅极氧化物层，第一导电层和栅极电介质层。导电条形成在栅介质层上。导电带被屏蔽层覆盖。使用屏蔽层作为屏蔽掩模蚀刻栅极介电层，第一导电层和栅极氧化物层，以形成用于存储单元的控制栅极。使用屏蔽层作为屏蔽掩模，将热氧化施加到整个基板上，以在基板的表面上形成隧道氧化物层，并隔离控制栅极的侧壁上的氧化物层。屏蔽层被去除。在导电条的两个侧壁上形成导电侧壁间隔物。每个导电侧壁间隔物覆盖隧道氧化物层的一部分，并且还通过隔离氧化物层与控制栅极电隔离，形成用于存储单元的浮动栅极。使用导电条和导电侧壁间隔物作为屏蔽掩模注入杂质，以在存储器单元的衬底上形成源区和漏区。

34. 发明授权

US5571739A Method for fabricating a read-only-memory (ROM) using a new ROM code mask process 失效
标题翻译：使用新的ROM代码掩码处理制造只读存储器（ROM）的方法
公开(公告)号：US5571739A
公开(公告)日：1996-11-05
申请号：US497883
申请日：1995-07-03
申请人： Gary Hong
发明人： Gary Hong
IPC分类号： H01L21/8246
CPC分类号： H01L27/11246 , Y10S438/981
摘要： A method of manufacturing an improved Read-Only-Memory (ROM) device, was achieved. The array of programmed ROM cells composed of field effect transistors (FETs) are fabricated having improved bit lines with lower resistance. The method utilizes the selective deposition of silicon oxide by a method of Liquid Phase Deposition (LPD) to form a thick insulating oxide layer over the gate oxide of the FET in the coded memory cells. The thick insulating oxide raises the threshold voltage of the FET, preventing the FET from turning on when a gate voltage is applied. The coding using a thick insulating oxide eliminates the need to code the ROM memory cells by ion implantation, and thereby prevents the counter-doping of the bit lines which results in the high bit line resistivity that degrades circuit performance.
摘要翻译：实现了改进的只读存储器（ROM）器件的制造方法。由场效应晶体管（FET）构成的编程ROM单元的阵列被制造成具有更低电阻的改进的位线。该方法利用液相沉积（LPD）的方法选择性沉积氧化硅，以在编码存储单元中的FET的栅极氧化物上形成厚的绝缘氧化物层。厚的绝缘氧化物提高FET的阈值电压，防止当施加栅极电压时FET导通。使用厚绝缘氧化物的编码消除了通过离子注入对ROM存储单元进行编码的需要，从而防止导致高位线电阻率的位线的反掺杂降低了电路性能。

35. 发明授权

US5550075A Ion implanted programmable cell for read only memory applications 失效
标题翻译：离子注入可编程单元，用于只读存储器应用
公开(公告)号：US5550075A
公开(公告)日：1996-08-27
申请号：US374967
申请日：1995-01-19
申请人： Chen-Chung Hsu , Gary Hong
发明人： Chen-Chung Hsu , Gary Hong
IPC分类号： H01L21/8229 , H01L27/102 , H01L21/265
CPC分类号： H01L21/8229 , H01L27/1021 , Y10S257/91 , Y10S438/981
摘要： A method for fabricating read only memory, (ROM), devices, has been developed. The programmable cell of this ROM device is comprised of a P/N diode, place in a N+ buried bit line. The diode formation is accomplished using outdiffusion from a P+ polysilicon wordline, that is in direct contact to a specific bit line region.
摘要翻译：已经开发了用于制造只读存储器（ROM），器件的方法。该ROM器件的可编程单元由P / N二极管组成，位于N +掩埋位线中。二极管形成是通过使用来自P +多晶硅字线的外扩散实现的，其与特定位线区域直接接触。

36. 发明授权

US5536673A Method for making dynamic random access memory (DRAM) cells having large capacitor electrode plates for increased capacitance 失效
标题翻译：制造具有用于增加电容的大电容器电极板的动态随机存取存储器（DRAM）单元的方法
公开(公告)号：US5536673A
公开(公告)日：1996-07-16
申请号：US507536
申请日：1995-07-26
申请人： Gary Hong , Jason Jyh-shyang Jenq
发明人： Gary Hong , Jason Jyh-shyang Jenq
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A method is desired for making an array of dynamic random access memory (DRAM) cells having stacked capacitors with increased capacitance. The method involves forming a bottom electrode having a lower and upper fin-shaped portion in which a vertical extension is formed on the lower fin-shape portion at the same time that the upper fin is formed. This increases the capacitance of the stacked capacitor. The bottom electrode is formed by patterning a thick expendable silicon oxide layer and an underlying doped polysilicon layer (lower fin portion). Another polysilicon layer (upper fin portion is conformally coated over the thick insulating layer and patterned with an etch mask, which is smaller than the patterned insulating layer. An anisotropic etch is performed that forms the upper fin portion, the vertical extension on the lower fin portion and electrically isolates the array of electrodes. The capacitors are then completed by removing the expendable oxide layer, forming a capacitor dielectric layer on the bottom electrode, and patterning a doped polysilicon layer for the top electrode of the stacked capacitor.
摘要翻译：期望制造具有增加的电容的堆叠电容器的动态随机存取存储器（DRAM）单元阵列的方法。该方法包括在形成上翅片的同时形成具有下翅片形状部分和上鳍形部分的底部电极，其中在下翅片形部分上形成垂直延伸部。这增加了堆叠电容器的电容。底部电极通过图案化厚的消耗性氧化硅层和下面的掺杂多晶硅层（下部翅片部分）来形成。另一个多晶硅层（上鳍部分被保形地涂覆在厚的绝缘层上，并用蚀刻掩模图案化，该蚀刻掩模小于图案化的绝缘层），进行各向异性蚀刻，形成上鳍部分，下翅片上的垂直延伸部部分并电隔离电极阵列，然后通过去除消耗性氧化物层，在底部电极上形成电容器电介质层，并对叠层电容器的顶部电极的掺杂多晶硅层进行构图来完成电容器。

37. 发明授权

US5529946A Process of fabricating DRAM storage capacitors 失效
标题翻译：制造DRAM存储电容器的过程
公开(公告)号：US5529946A
公开(公告)日：1996-06-25
申请号：US497270
申请日：1995-06-30
申请人： Gary Hong
发明人： Gary Hong
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91 , Y10S148/014
摘要： A process of fabricating the storage capacitor for a dynamic random access memory cell which includes a transistor with gate electrode and source/drain regions on a surface of a substrate. The process forms a polysilicon layer which is coupled to one of the source/drain regions, over the transistor structure. A mask is formed to cover the planned capacitor area, and then the non-masked portion of the polysilicon layer is removed. Liquid phase deposition oxide is formed on the area not masked by the mask, and then the mask is stripped. A polysilicon sidewall spacer is formed on the sidewalls of the LPD oxide, and connects with the remaining polysilicon layer to jointly form a first capacitor electrode. The LPD oxide is removed, followed by forming a dielectric layer along the surface of the first capacitor electrode. A second capacitor electrode made from polysilicon is formed along the surface of the dielectric layer to complete the storage capacitor structure.
摘要翻译：制造用于动态随机存取存储单元的存储电容器的过程包括在基板的表面上具有栅电极和源/漏区的晶体管。该工艺形成多晶硅层，该多晶硅层在晶体管结构上耦合到源/漏区中的一个。形成掩模以覆盖预定的电容器区域，然后去除多晶硅层的未屏蔽部分。在未被掩模掩蔽的区域上形成液相沉积氧化物，然后剥离掩模。在LPD氧化物的侧壁上形成多晶硅侧壁间隔物，并与剩余的多晶硅层连接，共同形成第一电容器电极。除去LPD氧化物，然后沿着第一电容器电极的表面形成电介质层。沿着电介质层的表面形成由多晶硅制成的第二电容器电极，以完成存储电容器结构。

38. 发明授权

US5489543A Method of forming a MOS device having a localized anti-punchthrough region 失效
标题翻译：形成具有局部防穿透区域的MOS器件的方法
公开(公告)号：US5489543A
公开(公告)日：1996-02-06
申请号：US347880
申请日：1994-12-01
申请人： Gary Hong
发明人： Gary Hong
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78 , H01L21/8234
CPC分类号： H01L29/66583 , H01L29/1083 , H01L29/66537 , H01L29/7833
摘要： A method of forming a MOS device having a localized anti-punchthrough region, which is adjacent to but is not in contact with source/drain regions of the MOS device. A trench is formed by depositing a conducting layer on an oxide layer located on a channel region of the MOS device. The trench is used as a self-alignment mask for a subsequent implantation process to form the localized anti-punchthrough region.
摘要翻译：一种形成具有与MOS器件的源极/漏极区域相邻但不接触的局部抗穿通区域的MOS器件的方法。通过在位于MOS器件的沟道区上的氧化物层上沉积导电层来形成沟槽。沟槽用作自对准掩模，用于随后的注入工艺以形成局部的抗穿透区域。

39. 发明授权

US5484744A Method for fabricating a stacked capacitor for dynamic random access memory cell 失效
标题翻译：制造用于动态随机存取存储单元的叠层电容器的方法
公开(公告)号：US5484744A
公开(公告)日：1996-01-16
申请号：US422291
申请日：1995-04-14
申请人： Gary Hong
发明人： Gary Hong
IPC分类号： H01L21/8242 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852
摘要： The present invention provides a method of fabricating a DRAM cell capacitor having an improved capacitance by increasing the surface area of the electrode plate. First, a first insulating layer, a second insulating layer, and a barrier layer are formed sequentially on a semiconductor substrate having source/drain regions. Next, a portion of the barrier layer is etched to form a first contact opening over one of the source/drain regions. A first sidewall spacer is formed on the sidewall of the first contact opening of the barrier layer. Similarly, a second contact opening is formed by etching the second insulating layer using the barrier layer and the first sidewall spacer as a mask, and a second sidewall spacer is formed on the sidewall of the second contact opening of the second insulating layer. Then, a third contact opening is formed by etching the first insulating layer using the first sidewall spacer, the second sidewall spacer, and the second insulating layer as a mask, meanwhile the barrier layer is also removed. After removing the second sidewall spacer, a first electrode plate is formed overlying the exposed surfaces of the first sidewall spacer, the second insulating layer, the first insulating layer, and the semiconductor substrate. Hence, the first electrode plate is connected to one of the source/drain regions through the third contact opening. Finally, a dielectric layer is formed on the first electrode plate, and a second electrode plate is formed on the dielectric layer to complete the capacitor fabrication.
摘要翻译：本发明提供通过增加电极板的表面积来制造具有改善的电容的DRAM单元电容器的方法。首先，在具有源极/漏极区域的半导体衬底上依次形成第一绝缘层，第二绝缘层和势垒层。接下来，蚀刻阻挡层的一部分以在源极/漏极区域之一上形成第一接触开口。第一侧壁间隔件形成在阻挡层的第一接触开口的侧壁上。类似地，通过使用阻挡层和第一侧壁间隔物作为掩模蚀刻第二绝缘层来形成第二接触开口，并且在第二绝缘层的第二接触开口的侧壁上形成第二侧壁间隔物。然后，通过使用第一侧壁间隔件，第二侧壁间隔件和第二绝缘层作为掩模蚀刻第一绝缘层来形成第三接触开口，同时还去除阻挡层。在去除第二侧壁间隔物之后，形成第一电极板，覆盖第一侧墙，第二绝缘层，第一绝缘层和半导体衬底的暴露表面。因此，第一电极板通过第三接触开口连接到源/漏区中的一个。最后，在第一电极板上形成电介质层，在电介质层上形成第二电极板以完成电容器制造。

40. 发明授权

US5473179A Method for improving erase characteristics and coupling ratios of buried bit line flash EPROM devices 失效
标题翻译：用于改善掩埋位线闪速EPROM器件的擦除特性和耦合比的方法
公开(公告)号：US5473179A
公开(公告)日：1995-12-05
申请号：US304693
申请日：1994-09-12
申请人： Gary Hong
发明人： Gary Hong
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/51 , H01L29/788 , H01L29/78
CPC分类号： H01L27/11517 , H01L27/115 , H01L29/511 , H01L29/7883 , H01L21/28211 , Y10S148/114
摘要： A new method of obtaining a consistent controllable tunnel oxide near the source/drain edge of a contactless memory cell is described. A thick gate oxide layer is grown on a semiconductor substrate. A first polysilicon layer is deposited overlying the thick gate oxide layer. A silicon nitride layer followed by a silicon oxide layer are deposited overlying the first polysilicon layer. The silicon oxide, silicon nitride, and first polysilicon layers are patterned and etched. Arsenic ions are implanted through the thick gate oxide layer into the substrate to form buried source and drain bit lines within the substrate. A second layer of silicon nitride is deposited over the patterned layers and anisotropically etched to form sidewall spacers. SATO (self-aligned thick oxide) oxidation is performed over the N+ area. The silicon nitride spacers are etched away whereby a portion of the thick gate oxide underlying the spacers is exposed. The silicon oxide layer is removed along with the exposed thick gate oxide. The thin tunnel oxide is regrown in the region where the silicon nitride spacers were removed. The silicon nitride layer is removed followed by deposition of a second layer of polysilicon overlying the first polysilicon layer. This layer is patterned such that it is overlying the SATO area to form the floating gate. An interpoly dielectric layer is deposited followed by a third polysilicon layer which is deposited and patterned to form the control gate completing formation of the memory cell.
摘要翻译：描述了在非接触式存储器单元的源极/漏极边缘附近获得一致的可控隧道氧化物的新方法。在半导体衬底上生长厚栅氧化层。沉积在厚栅极氧化物层上的第一多晶硅层。在第一多晶硅层上沉积氮化硅层，随后是氧化硅层。氧化硅，氮化硅和第一多晶硅层被图案化和蚀刻。将砷离子通过厚栅极氧化物层注入到衬底中，以在衬底内形成掩埋源极和漏极位线。第二层氮化硅沉积在图案化层上并各向异性蚀刻以形成侧壁间隔物。在N +区域上进行SATO（自对准厚氧化物）氧化。蚀刻氮化硅间隔物，由此暴露间隔物下方的厚栅极氧化物的一部分。氧化硅层与暴露的厚栅氧化物一起被去除。在去除氮化硅间隔物的区域中再生长薄的氧化隧道。去除氮化硅层，然后沉积覆盖在第一多晶硅层上的第二多晶硅层。该层被图案化，使得它覆盖在SATO区域上以形成浮动栅极。沉积多层介电层，随后沉积和图案化第三多晶硅层，以形成完成存储单元形成的控制栅极。

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