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31. 发明授权

US08357561B2 Method of fabricating backside illuminated image sensor 有权
标题翻译：制造背面照明图像传感器的方法
公开(公告)号：US08357561B2
公开(公告)日：2013-01-22
申请号：US13044407
申请日：2011-03-09
申请人： Shih-Chi Fu , Gwo-Yuh Shiau , Liang-Lung Yao , Yuan-Chih Hsieh , Feng-Jia Shiu
发明人： Shih-Chi Fu , Gwo-Yuh Shiau , Liang-Lung Yao , Yuan-Chih Hsieh , Feng-Jia Shiu
IPC分类号： H01L31/18 , H01L21/71 , H01L31/0232
CPC分类号： H01L27/14689 , H01L27/14609 , H01L27/14621 , H01L27/14627 , Y10S438/977
摘要： A method for fabricating a backside illuminated image sensor is provided. An exemplary method can include providing a substrate having a front surface and a back surface; forming an alignment mark at the front surface of the substrate, wherein the alignment mark is detectable for alignment from the back surface; and processing the substrate from the back surface by performing registration from the back surface and using the alignment mark as a reference.
摘要翻译：提供了制造背面照明图像传感器的方法。示例性方法可以包括提供具有前表面和后表面的基底; 在基板的前表面形成对准标记，其中对准标记可从后表面对准检测; 并且通过从背面进行配准并使用对准标记作为基准，从背面处理基板。

32. 发明申请

US20100087029A1 METHOD OF FABRICATING BACKSIDE ILLUMINATED IMAGE SENSOR 有权
标题翻译：背景照明图像传感器的制作方法
公开(公告)号：US20100087029A1
公开(公告)日：2010-04-08
申请号：US12634080
申请日：2009-12-09
申请人： Shih-Chi Fu , Gwo-Yuh Shiau , Liang-Lung Yao , Yuan-Chih Hsieh , Feng-Jia Shiu
发明人： Shih-Chi Fu , Gwo-Yuh Shiau , Liang-Lung Yao , Yuan-Chih Hsieh , Feng-Jia Shiu
IPC分类号： H01L31/18
CPC分类号： H01L27/14689 , H01L27/14609 , H01L27/14621 , H01L27/14627 , Y10S438/977
摘要： A method for fabricating a backside illuminated image sensor is provided. An exemplary method can include providing a substrate with a front surface and a back surface; forming a first alignment mark for global alignment on the front surface of the substrate; forming a second alignment mark for fine alignment in a clear-out region on the front surface of the substrate; aligning the substrate from the back surface using the first alignment mark; and removing a portion of the back surface of the substrate at the clear-out region for locating the second alignment mark.
摘要翻译：提供了制造背面照明图像传感器的方法。示例性方法可以包括提供具有前表面和后表面的基底; 在所述基板的前表面上形成用于全局对准的第一对准标记; 形成用于在所述基板的前表面上的透明区域中精细对准的第二对准标记; 使用第一对准标记从背面对准基板; 以及在所述清除区域处去除所述基板的背面的一部分以定位所述第二对准标记。

33. 发明申请

US20070207566A1 Method of fabricating backside illuminated image sensor 有权
标题翻译：制造背面照明图像传感器的方法
公开(公告)号：US20070207566A1
公开(公告)日：2007-09-06
申请号：US11369054
申请日：2006-03-06
申请人： Shih-Chi Fu , Gwo-Yuh Shiau , Liang-Lung Yao , Yuan-Chih Hsieh , Feng-Jia Shiu
发明人： Shih-Chi Fu , Gwo-Yuh Shiau , Liang-Lung Yao , Yuan-Chih Hsieh , Feng-Jia Shiu
IPC分类号： H01L21/00
CPC分类号： H01L27/14689 , H01L27/14609 , H01L27/14621 , H01L27/14627 , Y10S438/977
摘要： A method for fabricating a back-side illuminated image sensor includes providing a semiconductor substrate having a front surface and back surface, providing a plurality of transistors, metal interconnects, and metal pads on front surface of the substrate, bonding a supporting layer to the front surface of the substrate, thinning-down the semiconductor substrate from the back surface, clearing-out a region of the semiconductor substrate from the back surface that covers a fine alignment mark by performing registration from the back surface and using a global alignment mark as a reference, and processing the back surface of the substrate by performing registration from the back surface and using the fine alignment mark as a reference.
摘要翻译：制造背面照明图像传感器的方法包括提供具有前表面和后表面的半导体衬底，在衬底的前表面上提供多个晶体管，金属互连和金属焊盘，将支撑层粘合到前面基板的表面，从背面减薄半导体基板，通过从后表面进行配准，从覆盖微细对准标记的背面清除半导体基板的区域，并使用全局对准标记作为通过从后表面进行配准并使用精细对准标记作为参考来处理衬底的背面。

34. 发明申请

US20110159631A1 METHOD OF FABRICATING BACKSIDE ILLUMINATED IMAGE SENSOR 有权
标题翻译：背景照明图像传感器的制作方法
公开(公告)号：US20110159631A1
公开(公告)日：2011-06-30
申请号：US13044407
申请日：2011-03-09
申请人： Shih-Chu Fu , Gwo-Yuh Shiau , Liang-Lung Yao , Yuan-Chih Hsieh , Feng-Jia Shiu
发明人： Shih-Chu Fu , Gwo-Yuh Shiau , Liang-Lung Yao , Yuan-Chih Hsieh , Feng-Jia Shiu
IPC分类号： H01L31/18 , H01L21/71 , H01L31/0232
CPC分类号： H01L27/14689 , H01L27/14609 , H01L27/14621 , H01L27/14627 , Y10S438/977
摘要： A method for fabricating a backside illuminated image sensor is provided. An exemplary method can include providing a substrate having a front surface and a back surface; forming an alignment mark at the front surface of the substrate, wherein the alignment mark is detectable for alignment from the back surface; and processing the substrate from the back surface by performing registration from the back surface and using the alignment mark as a reference.
摘要翻译：提供了制造背面照明图像传感器的方法。示例性方法可以包括提供具有前表面和后表面的基底; 在基板的前表面形成对准标记，其中对准标记可从后表面对准检测; 并且通过从背面进行配准并使用对准标记作为基准，从背面处理基板。

35. 发明授权

US6077756A Overlay target pattern and algorithm for layer-to-layer overlay metrology for semiconductor processing 失效
标题翻译：覆盖目标模式和算法用于层间覆盖测量用于半导体处理
公开(公告)号：US6077756A
公开(公告)日：2000-06-20
申请号：US66015
申请日：1998-04-24
申请人： Hua-Tai Lin , Gwo-Yuh Shiau , Pin-Ting Wang
发明人： Hua-Tai Lin , Gwo-Yuh Shiau , Pin-Ting Wang
IPC分类号： H01L23/544 , H01L21/76
CPC分类号： H01L22/34 , Y10S438/975
摘要： Novel overlay targets and an algorithm metrology are provided that minimize the overlay measurement error for fabricating integrated circuits. The method is particularly useful for accurately measuring layer-to-layer overlay on a substrate having material layers, such insulating, polysilicon, and metal layers that have asymmetric profiles over the overlay targets resulting from asymmetric deposition or chemical/mechanically polishing. The novel method involves forming a triangular-shaped first overlay target in a first material layer on a substrate. A second material layer, having the asymmetric profile is formed over the first material layer. During patterning of the second material layer, smaller triangular-shaped second overlay target are etched. The vertices of the smaller second overlay targets are aligned to the midpoints of the sides of the first overlay target, which are less sensitive to the asymmetries in the second material layer. An algorithm is then used to determine the positions of the centroids of the first and second overlay targets, which coincide with perfect alignment. The distance between the two centroids is the degree of layer-to-layer misalignment of the two material layers.
摘要翻译：提供了新的覆盖目标和算法计量，可最大限度地减少用于制造集成电路的覆盖测量误差。该方法特别适用于在具有材料层的衬底上精确测量层间覆盖层，这种绝缘层，多晶硅层和金属层在由不对称沉积或化学/机械抛光产生的覆盖目标上具有不对称分布。该新方法涉及在基底上的第一材料层中形成三角形的第一覆盖目标。具有不对称轮廓的第二材料层形成在第一材料层上。在第二材料层的图案化期间，蚀刻较小的三角形的第二覆盖靶。较小的第二覆盖目标的顶点与第一覆盖目标的边的中点对准，其对第二材料层中的不对称性较不敏感。然后使用算法来确定第一和第二覆盖目标的质心的位置，其与完美对准重合。两个质心之间的距离是两层材料层的层间失准程度。

36. 发明授权

US5326794A Barbituric acid-modified bismaleimide with diamine and polyisocyanate-modified epoxy resin 失效
标题翻译：巴比妥酸改性双马来酰亚胺与二胺和多异氰酸酯改性环氧树脂
公开(公告)号：US5326794A
公开(公告)日：1994-07-05
申请号：US911692
申请日：1992-07-10
申请人： Jing-Pin Pan , Chuen-Chyr Chen , Gwo-Yuh Shiau , Ker-Ming Chen
发明人： Jing-Pin Pan , Chuen-Chyr Chen , Gwo-Yuh Shiau , Ker-Ming Chen
IPC分类号： C08L63/00 , C08L79/08 , H05K1/03 , C08L63/02 , C08K5/07 , C08L63/04 , C08L63/06
CPC分类号： H05K1/0353 , C08L63/00 , C08L79/085
摘要： A process for manufacturing a high glass transition temperature printed circuit board comprising blending a modified bismaleimide resin into a modified epoxy resin is disclosed. Particularly the material is manufactured by blending a bismaleimide resin reacted with barbituric acid and its derivative thereof and an epoxy resin with an oxazolidone ring resulting from the reaction of a polyisocyanate and an epoxy resin modified with a secondary diamine and followed by curing. The resultant product has a high glass transition temperature, a good adhesion, flame retardancy, and a low bromine content.
摘要翻译：公开了一种制造高玻璃化转变温度印刷电路板的方法，其包括将改性双马来酰亚胺树脂掺混到改性环氧树脂中。特别地，该材料通过将与巴比妥酸及其衍生物反应的双马来酰亚胺树脂与环氧树脂与由多异氰酸酯和经二胺改性的环氧树脂反应得到的恶唑烷酮环并随后固化而制得。所得产物具有高玻璃化转变温度，良好的粘合性，阻燃性和低溴含量。

37. 发明授权

US06803291B1 Method to preserve alignment mark optical integrity 有权
标题翻译：保持对准标记光学完整性的方法
公开(公告)号：US06803291B1
公开(公告)日：2004-10-12
申请号：US10394089
申请日：2003-03-20
申请人： Shih-Chi Fu , Feng-Jia Shih , Chia-Tung Ho , Chih-Ta Wu , Ching-Sen Kuo , Jieh-Jang Chen , Gwo-Yuh Shiau , Chia-Shiung Tsia
发明人： Shih-Chi Fu , Feng-Jia Shih , Chia-Tung Ho , Chih-Ta Wu , Ching-Sen Kuo , Jieh-Jang Chen , Gwo-Yuh Shiau , Chia-Shiung Tsia
IPC分类号： H01L2176
CPC分类号： H01L21/76229 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method for protecting an alignment mark area during a CMP process including forming at least a first material layer over a process surface of a semiconductor wafer including active areas and alignment mark trenches formed in the at least one alignment mark area; forming at least a second material layer over the first material layer including the active areas and the at least one alignment mark area; lithographically patterning and etching the at least a second material layer to form at least a plurality lines of the at least a second material layer adjacent to the alignment mark trenches; and, carrying out a CMP process to remove at least a portion of the at least a second material layer.
摘要翻译：一种用于在CMP工艺期间保护对准标记区域的方法，包括在半导体晶片的工艺表面上形成至少第一材料层，所述半导体晶片包括形成在所述至少一个对准标记区域中的有源区和对准标记沟槽; 在包括所述有源区域和所述至少一个对准标记区域的所述第一材料层上形成至少第二材料层; 对所述至少第二材料层进行光刻图案化和蚀刻，以形成与所述对准标记沟槽相邻的所述至少第二材料层的至少多条线; 以及执行CMP处理以去除所述至少第二材料层的至少一部分。

38. 发明授权

US5985363A Method of providing uniform photoresist coatings for tight control of image dimensions 失效
标题翻译：提供均匀的光刻胶涂层以紧实控制图像尺寸的方法
公开(公告)号：US5985363A
公开(公告)日：1999-11-16
申请号：US814129
申请日：1997-03-10
申请人： Gwo-Yuh Shiau , Shinn-Jhy Lian , Daniel Hao-Tien Lee , Li-Ming Wang , Hsiang-Wei Tseng
发明人： Gwo-Yuh Shiau , Shinn-Jhy Lian , Daniel Hao-Tien Lee , Li-Ming Wang , Hsiang-Wei Tseng
IPC分类号： G03F7/16 , H01L21/312 , B05D3/12 , B05D3/02 , H01L21/31
CPC分类号： G03F7/162 , H01L21/312
摘要： A method for providing a uniform coating of photoresist over substrate for defining high density integrated device and circuit patterns. This is accomplished by applying the photoresist onto the substrate in multiple, separate dispensing steps and leveling spins to attain the designed thickness uniformly over substrate having high topographic surfaces, thereby preserve the integrity of the critical dimension for multi-level alignments used in the fabrication of integrated devices and circuits.
摘要翻译：一种用于在衬底上提供均匀的光致抗蚀剂涂层以定义高密度集成器件和电路图案的方法。这通过在多个单独的分配步骤和调平旋转中将光致抗蚀剂施加到基板上来实现，以在具有高地形表面的基板上均匀地获得设计的厚度，从而保持制造中使用的多级对准的临界尺寸的完整性集成器件和电路。

39. 发明授权

US08847319B2 Dummy structure for multiple gate dielectric interface and methods 有权
标题翻译：多栅介质接口的虚拟结构和方法
公开(公告)号：US08847319B2
公开(公告)日：2014-09-30
申请号：US13416093
申请日：2012-03-09
申请人： Huei-Ru Liu , Chien-Chih Chou , Kong-Beng Thei , Gwo-Yuh Shiau
发明人： Huei-Ru Liu , Chien-Chih Chou , Kong-Beng Thei , Gwo-Yuh Shiau
IPC分类号： H01L23/62
CPC分类号： H01L29/42364 , H01L21/823814 , H01L21/82385 , H01L21/823857 , H01L29/51
摘要： Dummy structures between a high voltage (HV) region and a low voltage (LV) region of a substrate are disclosed, along with methods of forming the dummy structures. An embodiment is a structure comprising a HV gate dielectric over a HV region of a substrate, a LV gate dielectric over a LV region of the substrate, and a dummy structure over a top surface of the HV gate dielectric. A thickness of the LV gate dielectric is less than a thickness of the HV gate dielectric. The dummy structure is on a sidewall of the HV gate dielectric.
摘要翻译：公开了衬底的高电压（HV）区域和低电压（LV）区域之间的虚拟结构以及形成虚拟结构的方法。一个实施例是包括在衬底的HV区域上的HV栅极电介质，在衬底的LV区域上的LV栅极电介质和在HV栅极电介质的顶表面上方的虚设结构的结构。 LV栅极电介质的厚度小于HV栅极电介质的厚度。虚拟结构位于HV栅极电介质的侧壁上。

40. 发明申请

US20130234244A1 Dummy Structure for Multiple Gate Dielectric Interface and Methods 有权
标题翻译：多栅极电介质界面和方法的虚拟结构
公开(公告)号：US20130234244A1
公开(公告)日：2013-09-12
申请号：US13416093
申请日：2012-03-09
申请人： Huei-Ru Liu , Chien-Chih Chou , Kong-Beng Thei , Gwo-Yuh Shiau
发明人： Huei-Ru Liu , Chien-Chih Chou , Kong-Beng Thei , Gwo-Yuh Shiau
IPC分类号： H01L27/088 , H01L21/283
CPC分类号： H01L29/42364 , H01L21/823814 , H01L21/82385 , H01L21/823857 , H01L29/51
摘要： Dummy structures between a high voltage (HV) region and a low voltage (LV) region of a substrate are disclosed, along with methods of forming the dummy structures. An embodiment is a structure comprising a HV gate dielectric over a HV region of a substrate, a LV gate dielectric over a LV region of the substrate, and a dummy structure over a top surface of the HV gate dielectric. A thickness of the LV gate dielectric is less than a thickness of the HV gate dielectric. The dummy structure is on a sidewall of the HV gate dielectric.
摘要翻译：公开了衬底的高电压（HV）区域和低电压（LV）区域之间的虚拟结构以及形成虚拟结构的方法。一个实施例是包括在衬底的HV区域上的HV栅极电介质，在衬底的LV区域上的LV栅极电介质和在HV栅极电介质的顶表面上方的虚设结构的结构。 LV栅极电介质的厚度小于HV栅极电介质的厚度。虚拟结构位于HV栅极电介质的侧壁上。

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