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31. 发明申请

US20050268048A1 System and method for using a plurality of heterogeneous processors in a common computer system 审中-公开
标题翻译：在普通计算机系统中使用多个异构处理器的系统和方法
公开(公告)号：US20050268048A1
公开(公告)日：2005-12-01
申请号：US11171757
申请日：2005-06-30
申请人： Harm Hofstee , Charles Johns , James Kahle
发明人： Harm Hofstee , Charles Johns , James Kahle
IPC分类号： G06F15/16 , G06F9/44 , G06F9/50 , G06F15/177 , G06F15/80 , H04L29/06 , H04L29/08 , G06F13/00
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A system for using a plurality of heterogeneous processors in a common computer system is presented. Each processor type in the heterogeneous group handles a particular instruction set. The processors share a common memory using a common bus. In one embodiment, one of the processor types accesses the memory using DMA instructions. In another embodiment, a cache for each type of processor is stored in the common memory pool. In one embodiment, one or more PowerPC processors shares a memory with one or more Synergistic Processing Complex (SPC). A common table is used to track and maintain memory for the various processors.
摘要翻译：提出了一种在普通计算机系统中使用多个异构处理器的系统。异构组中的每个处理器类型处理特定的指令集。处理器使用公共总线共享共享内存。在一个实施例中，处理器类型之一使用DMA指令访问存储器。在另一个实施例中，用于每种类型的处理器的高速缓存存储在公共存储器池中。在一个实施例中，一个或多个PowerPC处理器与一个或多个协同处理复合体（SPC）共享存储器。通用表用于跟踪和维护各种处理器的内存。

32. 发明申请

US20070288701A1 System and Method for Using a Plurality of Heterogeneous Processors in a Common Computer System 审中-公开
标题翻译：在普通计算机系统中使用多个异构处理器的系统和方法
公开(公告)号：US20070288701A1
公开(公告)日：2007-12-13
申请号：US11841852
申请日：2007-08-20
申请人： Harm Hofstee , Charles Johns , James Kahle
发明人： Harm Hofstee , Charles Johns , James Kahle
IPC分类号： G06F13/00
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A system for using a plurality of heterogeneous processors in a common computer system is presented. Each processor type in the heterogeneous group handles a particular instruction set. The processors share a common memory using a common bus. In one embodiment, one of the processor types accesses the memory using DMA instructions. In another embodiment, a cache for each type of processor is stored in the common memory pool. In one embodiment, one or more PowerPC processors shares a memory with one or more Synergistic Processing Complex (SPC). A common table is used to track and maintain memory for the various processors.
摘要翻译：提出了一种在普通计算机系统中使用多个异构处理器的系统。异构组中的每个处理器类型处理特定的指令集。处理器使用公共总线共享共享内存。在一个实施例中，处理器类型之一使用DMA指令访问存储器。在另一个实施例中，用于每种类型的处理器的高速缓存存储在公共存储器池中。在一个实施例中，一个或多个PowerPC处理器与一个或多个协同处理复合体（SPC）共享存储器。通用表用于跟踪和维护各种处理器的内存。

33. 发明申请

US20060190614A1 Non-homogeneous multi-processor system with shared memory 失效
公开(公告)号：US20060190614A1
公开(公告)日：2006-08-24
申请号：US11065537
申请日：2005-02-24
申请人： Erik Altman , Peter Capek , Michael Gschwind , Charles Johns , Harm Hofstee , Martin Hopkins , James Kahle , Sumedh Sathaye , John-David Wellman
发明人： Erik Altman , Peter Capek , Michael Gschwind , Charles Johns , Harm Hofstee , Martin Hopkins , James Kahle , Sumedh Sathaye , John-David Wellman
IPC分类号： G06F15/16
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

34. 发明申请

US20060179168A1 System and method for flexible multiple protocols 有权
标题翻译：灵活多协议的系统和方法
公开(公告)号：US20060179168A1
公开(公告)日：2006-08-10
申请号：US11050022
申请日：2005-02-03
申请人： Scott Clark , Charles Johns , James Kahle
发明人： Scott Clark , Charles Johns , James Kahle
IPC分类号： G06F3/00
CPC分类号： G06F13/385
摘要： A system and method for flexible multiple protocols are presented. A device's logical layer may be dynamically configured on a per interface basis to communicate with external devices in a coherent or a non-coherent mode. In coherent mode, commands such as coherency protocol, system commands, and snoop response pass from the device's internal system bus to an external device, thereby creating a logical extension of the devices internal system bus. In non-coherent mode, the input-output bus unit receives commands from the internal system bus and generates non-coherent input-output commands, which are eventually received by an external device.
摘要翻译：介绍了灵活多协议的系统和方法。可以在每个接口的基础上动态地配置设备的逻辑层，以以相干或非相干模式与外部设备进行通信。在相干模式下，诸如一致性协议，系统命令和侦听响应的命令从设备的内部系统总线传递到外部设备，从而创建设备内部系统总线的逻辑扩展。在非相干模式下，输入 - 输出总线单元从内部系统总线接收命令，并产生最终由外部设备接收的非相干输入 - 输出命令。

35. 发明申请

US20060155955A1 SIMD-RISC processor module 审中-公开
标题翻译： SIMD-RISC处理器模块
公开(公告)号：US20060155955A1
公开(公告)日：2006-07-13
申请号：US11032194
申请日：2005-01-10
申请人： Michael Gschwind , Charles Johns , Harm Hofstee , James Kahle
发明人： Michael Gschwind , Charles Johns , Harm Hofstee , James Kahle
IPC分类号： G06F15/00
CPC分类号： G06F15/8007 , G06F13/1663
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.
摘要翻译：提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。每个软件单元在网络上唯一标识。

36. 发明申请

US20050097280A1 System and method for sharing memory by Heterogen ous processors 有权
标题翻译： Heterogen处理器共享内存的系统和方法
公开(公告)号：US20050097280A1
公开(公告)日：2005-05-05
申请号：US10697897
申请日：2003-10-30
申请人： Harm Hofstee , Charles Johns , James Kahle
发明人： Harm Hofstee , Charles Johns , James Kahle
IPC分类号： G06F12/00 , G06F12/10
CPC分类号： G06F12/0284 , G06F13/1652
摘要： A system for sharing memory by heterogeneous processors, each of which is adapted to process its own instruction set, is presented. A common bus is used to couple the common memory to the various processors. In one embodiment, a cache for more than one of the processors is stored in the shared memory. In another embodiment, some of the processors include a local memory area that is mapped to the shared memory pool. In yet another embodiment, local memory included on one or more of the processors is partially shared so that some of the local memory is mapped to the shared memory area, while remaining memory in the local memory is private to the particular processor.
摘要翻译：提出了一种用于通过异构处理器共享存储器的系统，每个处理器适于处理其自身的指令集。公共总线用于将公共存储器耦合到各种处理器。在一个实施例中，用于多于一个处理器的高速缓存存储在共享存储器中。在另一个实施例中，一些处理器包括映射到共享存储器池的本地存储器区域。在另一个实施例中，包括在一个或多个处理器中的本地存储器被部分地共享，使得一些本地存储器被映射到共享存储器区域，而本地存储器中的剩余存储器对于特定处理器是专用的。

37. 发明申请

US20050097231A1 System and method for a configurable interface controller 有权
标题翻译：可配置接口控制器的系统和方法
公开(公告)号：US20050097231A1
公开(公告)日：2005-05-05
申请号：US10697903
申请日：2003-10-30
申请人： Harm Hofstee , Charles Johns , James Kahle
发明人： Harm Hofstee , Charles Johns , James Kahle
IPC分类号： G06F3/00 , G06F3/14 , G09G5/14
CPC分类号： G06F3/1423 , G06F3/1454 , G09G5/14 , G09G2360/121 , G09G2370/04
摘要： A flexible input/output controller logic interfaces with existing input/output controllers (IOC's) in order to configure the amount of data sent to and received from the IOC's. The flexible I/O interface receives data from a component at a rate determined by the particular component. The flexible I/O interface then feeds the received data to a traditional I/O controller at a rate suitable for the I/O controller. Thus, the interface to the individual I/O controllers is maintained. The flexible I/O logic balances bandwidth between a plurality of individual I/O controllers in order to better utilize the overall system I/O bandwidth. In one embodiment, the I/O configuration managed by the flexible I/O logic is determined during system-build, while in another embodiment, the I/O configuration is set during system initialization.
摘要翻译：灵活的输入/输出控制器逻辑与现有的输入/输出控制器（IOC）进行接口，以便配置向国际奥委会发送和接收的数据量。灵活的I / O接口以特定组件确定的速率从组件接收数据。然后，灵活的I / O接口以适合于I / O控制器的速率将接收的数据馈送到传统的I / O控制器。因此，保持与各个I / O控制器的接口。灵活的I / O逻辑平衡多个独立I / O控制器之间的带宽，以便更好地利用整个系统I / O带宽。在一个实施例中，在系统构建期间确定由灵活I / O逻辑管理的I / O配置，而在另一实施例中，在系统初始化期间设置I / O配置。

38. 发明申请

US20050138621A1 Method of resource allocation using an access control mechanism 失效
标题翻译：使用访问控制机制的资源分配方法
公开(公告)号：US20050138621A1
公开(公告)日：2005-06-23
申请号：US10738720
申请日：2003-12-17
申请人： Scott Clark , Michael Day , Charles Johns , Andrew Wottreng
发明人： Scott Clark , Michael Day , Charles Johns , Andrew Wottreng
IPC分类号： G06F9/46
CPC分类号： G06F9/52 , G06F9/5011
摘要： A method and apparatus are provided for efficiently managing limited resources is a given computer system. The system utilizes a token manager that assigns tokens to groups of associated requestors. The tokens are then utilized by the requesters to occupy the given resource. The allocation of these tokens, thus, prevents such problems as denial of service due to a lack of available resources.
摘要翻译：提供用于有效地管理有限资源的方法和装置是给定的计算机系统。该系统利用令牌管理器，将令牌分配给相关联的请求者的组。然后请求者利用令牌来占用给定的资源。因此，这些令牌的分配可以防止由于缺乏可用资源而导致拒绝服务的问题。

39. 发明申请

US20070088866A1 Destructive DMA lists 失效
标题翻译：破坏性DMA列表
公开(公告)号：US20070088866A1
公开(公告)日：2007-04-19
申请号：US11252532
申请日：2005-10-18
申请人： Michael Day , Charles Johns , Barry Minor
发明人： Michael Day , Charles Johns , Barry Minor
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A buffer, a method, and a computer program product for DMA transfers are provided that are designed to save memory space within a local memory of a processor. The buffer is a return buffer with a portion reserved for DMA lists. A DMA controller accomplishes DMA transfers by: reading address elements from a DMA list located in the DMA list portion; reading the corresponding data from system memory; and copying the corresponding data to the return buffer portion. This buffer saves space because when the buffer begins to fill up the corresponding return data can overwrite the data in the DMA list. Accordingly, the DMA list overlays on top of the return buffer, such that the return data can destruct the DMA list and the extra storage space for the DMA list is saved.
摘要翻译：提供了用于DMA传输的缓冲器，方法和计算机程序产品，其被设计为在处理器的本地存储器内节省存储器空间。缓冲区是具有为DMA列表保留的部分的返回缓冲区。 DMA控制器通过以下方式完成DMA传输：从位于DMA列表部分的DMA列表读取地址元素; 从系统内存读取相应的数据; 并将相应的数据复制到返回缓冲器部分。此缓冲区可节省空间，因为当缓冲区开始填满相应的返回数据时，可以覆盖DMA列表中的数据。因此，DMA列表覆盖在返回缓冲器的顶部，使得返回数据可以破坏DMA列表，并且保存DMA列表的额外的存储空间。

40. 发明申请

US20050160229A1 Method and apparatus for preloading translation buffers 审中-公开
标题翻译：用于预加载翻译缓冲区的方法和装置
公开(公告)号：US20050160229A1
公开(公告)日：2005-07-21
申请号：US10759941
申请日：2004-01-16
申请人： Charles Johns , Michael Day , Jonathan DeMent
发明人： Charles Johns , Michael Day , Jonathan DeMent
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/1027 , G06F2212/654 , G06F2212/684
摘要： A method and an apparatus are provided for efficiently managing the operation of a translation buffer. A software and hardware apparatus and method are utilized to pre-load a translation buffer to prevent poor operation as a result of slow warming of a cache.
摘要翻译：提供了一种用于有效地管理翻译缓冲器的操作的方法和装置。使用软件和硬件装置和方法来预加载翻译缓冲器，以防止由于缓存缓慢升温而造成的不良操作。

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