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31. 发明申请

US20110294273A1 Method and Layout of Semiconductor Device with Reduced Parasitics 有权
标题翻译：具有减少寄生性的半导体器件的方法和布局
公开(公告)号：US20110294273A1
公开(公告)日：2011-12-01
申请号：US13087102
申请日：2011-04-14
申请人： Albert Birner , Qiang Chen
发明人： Albert Birner , Qiang Chen
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/0661 , H01L29/402 , H01L29/4175 , H01L29/4238 , H01L29/456 , H01L29/4933 , H01L29/4941 , H01L29/7823
摘要： An semiconductor device is disclosed. The device includes a semiconductor body, a layer of insulating material disposed over the semiconductor body, and a region of gate electrode material disposed over the layer of insulating material. Also included are a source region adjacent to gate region and a drain region adjacent to the gate region. A gate connection is disposed over the semiconductor body, wherein the gate connection includes a region of gate electrode material electrically coupling a contact region to the gate electrode. An insulating region is disposed on the semiconductor body beneath the gate connection.
摘要翻译：公开了一种半导体器件。该器件包括半导体本体，设置在半导体本体上的绝缘材料层以及设置在绝缘材料层上的栅电极材料区域。还包括与栅极区域相邻的源极区域和与栅极区域相邻的漏极区域。栅极连接设置在半导体本体上，其中栅极连接包括将接触区域电耦合到栅电极的栅电极材料区域。绝缘区域设置在栅极连接下方的半导体本体上。

32. 发明申请

US20070105302A1 Integrated circuit formed on a semiconductor substrate 审中-公开
标题翻译：集成电路形成在半导体衬底上
公开(公告)号：US20070105302A1
公开(公告)日：2007-05-10
申请号：US11269897
申请日：2005-11-09
申请人： Albert Birner , Andreas Weber , Frank Ludwig , Jorg Radecker , Kimberly Wilson , Kerstin Mothes
发明人： Albert Birner , Andreas Weber , Frank Ludwig , Jorg Radecker , Kimberly Wilson , Kerstin Mothes
IPC分类号： H01L21/76 , H01L21/8242
CPC分类号： H01L27/10861 , H01L27/10844 , H01L27/1087
摘要： An integrated circuit is provided, which is formed on a semiconductor substrate. The integrated circuit comprises electronic elements and isolation elements, wherein the electronic elements and the isolation elements are arranged at a top surface of the semiconductor substrate. The isolation elements each are arranged between electronic elements and electrically isolate the electronic elements from each other. Furthermore, the isolation elements comprise an upper part and a lower part, wherein the upper part is broader than the lower part.
摘要翻译：提供了形成在半导体衬底上的集成电路。集成电路包括电子元件和隔离元件，其中电子元件和隔离元件布置在半导体衬底的顶表面。隔离元件各自布置在电子元件之间并将电子元件彼此电隔离。此外，隔离元件包括上部和下部，其中上部比下部更宽。

33. 发明授权

US08035140B2 Method and layout of semiconductor device with reduced parasitics 有权
标题翻译：减少寄生效应的半导体器件的方法和布局
公开(公告)号：US08035140B2
公开(公告)日：2011-10-11
申请号：US11828944
申请日：2007-07-26
申请人： Albert Birner , Qiang Chen
发明人： Albert Birner , Qiang Chen
IPC分类号： H01L29/76
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/0661 , H01L29/402 , H01L29/4175 , H01L29/4238 , H01L29/456 , H01L29/4933 , H01L29/4941 , H01L29/7823
摘要： An semiconductor device is disclosed. The device includes a semiconductor body, a layer of insulating material disposed over the semiconductor body, and a region of gate electrode material disposed over the layer of insulating material. Also included are a source region adjacent to gate region and a drain region adjacent to the gate region. A gate connection is disposed over the semiconductor body, wherein the gate connection includes a region of gate electrode material electrically coupling a contact region to the gate electrode. An insulating region is disposed on the semiconductor body beneath the gate connection.
摘要翻译：公开了一种半导体器件。该器件包括半导体本体，设置在半导体本体上的绝缘材料层以及设置在绝缘材料层上的栅电极材料区域。还包括与栅极区域相邻的源极区域和与栅极区域相邻的漏极区域。栅极连接设置在半导体本体上，其中栅极连接包括将接触区域电耦合到栅电极的栅电极材料区域。绝缘区域设置在栅极连接下方的半导体本体上。

34. 发明授权

US07772123B2 Through substrate via semiconductor components 有权
标题翻译：通过半导体元件的基板
公开(公告)号：US07772123B2
公开(公告)日：2010-08-10
申请号：US12135059
申请日：2008-06-06
申请人： Albert Birner , Uwe Hoeckele , Thomas Kunstmann , Uwe Seidel
发明人： Albert Birner , Uwe Hoeckele , Thomas Kunstmann , Uwe Seidel
IPC分类号： H01L21/311
CPC分类号： H01L21/76877 , H01L21/76898 , H01L23/481 , H01L2224/0401 , H01L2224/04042 , H01L2224/0557 , H01L2224/05571 , H01L2224/13009 , H01L2224/13025 , H01L2224/16 , H01L2924/00014 , H01L2924/0002 , H01L2924/01019 , H01L2924/01068 , H01L2924/01079 , H01L2924/00012 , H01L2224/05552
摘要： A structure and method of forming through substrate vias in forming semiconductor components are described. In one embodiment, the invention describes a method of forming the through substrate via by filling an opening with a first fill material and depositing a first insulating layer over the first fill material, the first insulating layer not being deposited on sidewalls of the fill material in the opening, wherein sidewalls of the first insulating layer form a gap over the opening. The method further includes forming a void by sealing the opening using a second insulating layer.
摘要翻译：描述了在形成半导体部件时通过衬底通孔形成的结构和方法。在一个实施例中，本发明描述了一种通过用第一填充材料填充开口形成通孔基底通孔的方法，并且在第一填充材料上沉积第一绝缘层，第一绝缘层未沉积在填充材料的侧壁上所述开口，其中所述第一绝缘层的侧壁在所述开口上形成间隙。该方法还包括通过使用第二绝缘层密封开口来形成空隙。

35. 发明申请

US20070105262A1 Method for fabricating an integrated circuit with a CMOS manufacturing process 审中-公开
标题翻译：利用CMOS制造工艺制造集成电路的方法
公开(公告)号：US20070105262A1
公开(公告)日：2007-05-10
申请号：US11270820
申请日：2005-11-10
申请人： Albert Birner , Andreas Weber , Olaf Storbeck , Michael Stadtmueller , Wieland Pethe
发明人： Albert Birner , Andreas Weber , Olaf Storbeck , Michael Stadtmueller , Wieland Pethe
IPC分类号： H01L21/00
CPC分类号： H01L21/76801 , H01L21/76832 , H01L21/76834 , H01L27/105 , H01L27/1052 , H01L27/10894
摘要： An integrated circuit, which is formed on a semiconductor substrate and which comprises front-end-of-line processed electronic elements and a back-end-of-line processed wiring on top of the electronic elements. The wiring interconnects the electronic elements. The integrated circuit further comprises a highly UV-absorbing layer between the electronic elements and the wiring.
摘要翻译：一种集成电路，其形成在半导体衬底上并且包括前端处理电子元件和在电子元件顶部的后端处理线。布线将电子元件互连。集成电路还包括在电子元件和布线之间的高度紫外线吸收层。

36. 发明授权

US07157371B2 Barrier layer and a method for suppressing diffusion processes during the production of semiconductor devices 有权
标题翻译：阻挡层以及在制造半导体器件期间抑制扩散过程的方法
公开(公告)号：US07157371B2
公开(公告)日：2007-01-02
申请号：US10653599
申请日：2003-09-02
申请人： Thomas Hecht , Uwe Schroeder , Harald Seidl , Martin Gutsche , Stefan Jakschik , Stephan Kudelka , Albert Birner
发明人： Thomas Hecht , Uwe Schroeder , Harald Seidl , Martin Gutsche , Stefan Jakschik , Stephan Kudelka , Albert Birner
IPC分类号： H01L21/44
CPC分类号： H01L27/11502 , H01L21/02178 , H01L21/02181 , H01L21/28061 , H01L21/31138 , H01L21/31604 , H01L21/3162 , H01L21/76802 , H01L21/76828 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L27/11507 , H01L28/57 , H01L29/0895 , H01L29/4941
摘要： A dielectric barrier layer composed of a metal oxide is applied in thin layers with a thickness of less than 20 nanometers in the course of processing semiconductor devices by sequential gas phase deposition or molecular beam epitaxy in molecular individual layers on differently structured base substrates. The method allows, inter alias, effective conductive diffusion barriers to be formed from a dielectric material, an optimization of the layer thickness of the barrier layer, an increase in the temperature budget for subsequent process steps, and a reduction in the effort for removing the temporary barrier layers.
摘要翻译：由金属氧化物构成的电介质阻挡层通过在不同结构的基底衬底上的分子单层中的顺序气相沉积或分子束外延处理半导体器件的过程中以小于20纳米的厚度施加。该方法允许间隔地从电介质材料形成有效的导电扩散阻挡层，优化阻挡层的层厚度，随后的工艺步骤的温度预算的增加以及用于去除临时阻隔层。

37. 发明申请

US20100230818A1 Through Substrate Via Semiconductor Components 有权
标题翻译：通过基板通过半导体元件
公开(公告)号：US20100230818A1
公开(公告)日：2010-09-16
申请号：US12790220
申请日：2010-05-28
申请人： Albert Birner , Uwe Hoeckele , Thomas Kunstmann , Uwe Seidel
发明人： Albert Birner , Uwe Hoeckele , Thomas Kunstmann , Uwe Seidel
IPC分类号： H01L23/48
CPC分类号： H01L21/76877 , H01L21/76898 , H01L23/481 , H01L2224/0401 , H01L2224/04042 , H01L2224/0557 , H01L2224/05571 , H01L2224/13009 , H01L2224/13025 , H01L2224/16 , H01L2924/00014 , H01L2924/0002 , H01L2924/01019 , H01L2924/01068 , H01L2924/01079 , H01L2924/00012 , H01L2224/05552
摘要： A structure and method of forming through substrate vias in forming semiconductor components are described. In one embodiment, the invention describes a method of forming a through substrate via by partially filling an opening with a fill material, and forming a first insulating layer over the first fill material thereby forming a gap over the opening. The method further includes forming a second insulating layer to close the gap thereby forming an enclosed cavity within the opening.
摘要翻译：描述了在形成半导体部件时通过衬底通孔形成的结构和方法。在一个实施例中，本发明描述了一种通过用填充材料部分地填充开口形成贯通衬底通孔的方法，并且在第一填充材料之上形成第一绝缘层，从而在开口上形成间隙。该方法还包括形成第二绝缘层以封闭间隙，从而在开口内形成封闭空腔。

38. 发明授权

US07208370B2 Method for fabricating a vertical transistor in a trench, and vertical transistor 有权
标题翻译：在沟槽中制造垂直晶体管的方法和垂直晶体管
公开(公告)号：US07208370B2
公开(公告)日：2007-04-24
申请号：US10484562
申请日：2002-07-08
申请人： Albert Birner , Joern Luetzen
发明人： Albert Birner , Joern Luetzen
IPC分类号： H01L21/8242
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10867 , H01L27/10876 , H01L29/66666
摘要： To fabricate a vertical transistor, a trench is provided, the side wall of which is formed by a semiconductor substrate in single crystal form and the base of which is formed by a polycrystalline semiconductor substrate. A transition region is arranged between the side wall and the base. A semiconductor layer is deposited so that an epitaxial semiconductor layer grows on the side wall and a semiconductor layer grows on the base, with a space remaining between these layers. The semiconductor layers are covered with a thin dielectric, which partially limits a flow of current, and the space is filled. During a subsequent heat treatment, dopants diffuse out of the conductive material into the epitaxial semiconductor layer, where they form a doping region. The thin dielectric limits the diffusion of the dopants into the semiconductor substrate and prevents the propagation of crystal lattice defects into the epitaxial semiconductor layer.
摘要翻译：为了制造垂直晶体管，设置沟槽，其沟槽由单晶形式的半导体衬底形成，其基底由多晶半导体衬底形成。过渡区域设置在侧壁和底座之间。沉积半导体层，使得外延半导体层在侧壁上生长并且半导体层在基底上生长，并且在这些层之间保留空间。半导体层被薄的电介质覆盖，其部分地限制了电流，并且填充了空间。在随后的热处理期间，掺杂剂从导电材料扩散到外延半导体层中，在其中它们形成掺杂区域。薄电介质限制掺杂剂到半导体衬底中的扩散，并防止晶格缺陷向外延半导体层的传播。

39. 发明申请

US20070037340A1 Fabrication method for fabricating a semiconductor structure and semiconductor structure 审中-公开
标题翻译：制造半导体结构和半导体结构的制造方法
公开(公告)号：US20070037340A1
公开(公告)日：2007-02-15
申请号：US11477577
申请日：2006-06-29
申请人： Albert Birner , Andreas Weber , Rolf Weis
发明人： Albert Birner , Andreas Weber , Rolf Weis
IPC分类号： H01L21/8238
CPC分类号： H01L21/76224 , H01L27/10873 , H01L29/1037
摘要： In a method for fabricating a semiconductor structure a semiconductor substrate comprising an active region with an uncovered top side is provided, at least one STI trench adjoining the active region is formed, and an STI divot is formed in the insulating filling. The at least one STI trench comprises an insulating filling extending to above the top side of the active region and the divot adjoins the active region and uncovers an edge of the uncovered top side of the active region. A hydrogen termination of the uncovered top side of the active region is formed and a heat treatment in a hydrogen atmosphere is carried out in order to form a rounding from the edge of the active region in such a way that the top side of the active region continuously merges into the STI divot.
摘要翻译：在制造半导体结构的方法中，提供包括具有未覆盖的顶侧的有源区的半导体衬底，形成与有源区邻接的至少一个STI沟槽，并且在绝缘填充物中形成STI纹。所述至少一个STI沟槽包括延伸到有源区的顶侧上方的绝缘填充物，并且所述突起邻接所述有源区，并且露出所述有源区的未覆盖的顶侧的边缘。形成有源区的未覆盖的顶侧的氢终端，并且在氢气氛中进行热处理，以便从有源区的边缘形成圆化，使得有源区的顶侧不断融入STI纹章。

40. 发明授权

US07144770B2 Memory cell and method for fabricating it 有权
标题翻译：记忆单元及其制造方法
公开(公告)号：US07144770B2
公开(公告)日：2006-12-05
申请号：US10980069
申请日：2004-11-03
申请人： Albert Birner , Matthias Foerster , Thomas Hecht , Michael Stadtmueller , Andreas Orth
发明人： Albert Birner , Matthias Foerster , Thomas Hecht , Michael Stadtmueller , Andreas Orth
IPC分类号： H01L21/8242
CPC分类号： H01L29/66181 , H01L29/945
摘要： The invention provides a method for fabricating a memory cell, a substrate (101) being provided, a trench-type depression (102) being etched into the substrate (101), a barrier layer (103) being deposited non-conformally in the trench-type depression (102), grain elements (104) being grown on the inner areas of the trench-type depression (102), a dielectric layer (202) being deposited on the surfaces of the grain elements and the inner areas of the trench-type depression, and a conduction layer being deposited on the dielectric layer, the grain elements (104) growing selectively on the inner areas (105) of the trench-type depression (102) in an electrode region (301) forming a lower region of the trench-type depression (102) and an amorphous silicon layer continuing to grow in a collar region (302) forming an upper region of the trench-type depression (102).
摘要翻译：本发明提供了一种用于制造存储单元的方法，提供了一种衬底（101），蚀刻到衬底（101）中的沟槽型凹陷（102），在沟槽中非保形地沉积的阻挡层（103）型凹陷（102），在沟槽型凹部（102）的内部区域上生长的晶粒元素（104），沉积在晶粒元素的表面上的介电层（202）和沟槽的内部区域型凹陷，并且导电层沉积在电介质层上，晶粒元素（104）选择性地生长在形成下部区域的电极区域（301）中的沟槽型凹陷（102）的内部区域（105）的沟槽型凹陷（102）和在形成沟槽型凹陷（102）的上部区域的凸缘区域（302）中继续生长的非晶硅层。

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