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31. 发明授权

US07986621B2 Apparatus and method to set the signaling rate for a plurality of data storage devices 失效
标题翻译：设置多个数据存储设备的信令速率的装置和方法
公开(公告)号：US07986621B2
公开(公告)日：2011-07-26
申请号：US11776450
申请日：2007-07-11
申请人： Brian James Cagno
发明人： Brian James Cagno
IPC分类号： H04J1/16
CPC分类号： G06F13/4022 , G06F3/061 , G06F3/0632 , G06F3/0635 , G06F3/0683
摘要： A signaling speed module wherein that signaling speed module sets the signaling rate for each of a plurality of data storage devices. In certain embodiments of the invention, the signaling speed module comprises a memory device encoded with a pre-determined signaling rate. In other embodiments of the invention, the signaling speed module comprises a speed selection module, wherein that speed selection module sets the signaling rate for each of a plurality of data storage devices.
摘要翻译：一种信令速度模块，其中所述信令速度模块为多个数据存储设备中的每一个设置信令速率。在本发明的某些实施例中，信令速度模块包括用预定信令速率编码的存储器件。在本发明的其他实施例中，信令速度模块包括速度选择模块，其中速度选择模块设置多个数据存储设备中的每一个的信令速率。

32. 发明申请

US20080178033A1 APPARATUS, SYSTEM, AND METHOD FOR RESETTING AN INTER-INTEGRATED CIRCUIT DATA LINE WITH A CLOCK LINE 失效
标题翻译：用时钟线复位内部集成电路数据线的装置，系统和方法
公开(公告)号：US20080178033A1
公开(公告)日：2008-07-24
申请号：US11626220
申请日：2007-01-23
申请人： Brian James Cagno , Kenny Nian Gan Qiu , Donald Scott Smith
发明人： Brian James Cagno , Kenny Nian Gan Qiu , Donald Scott Smith
IPC分类号： G06F1/06
CPC分类号： G06F1/24
摘要： An apparatus, system, and method are disclosed for resetting an inter-integrated circuit data line with a clock line. A hang module detects that a data line that carries data between an I2C bus master and an I2C bus slave is hung, wherein the I2C bus master and I2C bus slave communicate over the data line and a clock line that carries a clock signal. The clock module increases a clock line frequency to a specified frequency in response to the detected data line hang. The pulse generation module transmits specified clock pulses from the I2C bus master to the I2C bus slave over the clock line at the specified increased frequency in response to the detected data line hang. A frequency detector module detects clock pulses at the specified increased frequency. A timer module detects the specified clock pulses at the specified increased frequency. A reset module resets the I2C bus slave in response detecting the specified clock pulses.
摘要翻译：公开了用时钟线重置集成电路数据线的装置，系统和方法。挂起模块检测到在I2C总线主机和I2C总线从站之间传送数据的数据线是挂起的，其中I2C总线主控和I2C总线从站通过数据线通信，时钟线通信一个时钟信号。响应于检测到的数据线挂起，时钟模块将时钟线频率增加到指定频率。脉冲发生模块响应于检测到的数据线挂起，以指定的增加频率通过时钟线将指定的时钟脉冲从I2C总线主机传输到I2C总线从器件。频率检测器模块以指定的增加频率检测时钟脉冲。定时器模块以指定的增加频率检测指定的时钟脉冲。响应检测指定的时钟脉冲，复位模块复位I2C总线从器件。

33. 发明申请

US20080071393A1 PERIODIC ROTATIONAL VIBRATION CHECK FOR STORAGE DEVICES TO COMPENSATE FOR VARYING LOADS 有权
标题翻译：用于存储设备的周期性旋转振动检查以补偿变化的负载
公开(公告)号：US20080071393A1
公开(公告)日：2008-03-20
申请号：US11467417
申请日：2006-08-25
申请人： Brian James Cagno , Kenton Coleman Green , Carl Evan Jones , Michael Desmond O'Connell
发明人： Brian James Cagno , Kenton Coleman Green , Carl Evan Jones , Michael Desmond O'Connell
IPC分类号： G05B13/02
CPC分类号： G11B27/36 , G05B13/0205
摘要： A periodic rotational vibration check for storage devices to compensate for varying loads is disclosed. A variable representing rotational vibration status is maintained in a rotational vibration log. The variable is processed to determine whether a storage device exhibits a rotational vibration issue. Workload analysis is performed to identify a change to the workloads run on physically separate hardware to resolve the rotational vibration issue and thus eliminate the need for more expensive hardware.
摘要翻译：公开了用于存储装置的周期性旋转振动检查以补偿变化的负载。表示旋转振动状态的变量保持在旋转振动对数中。处理变量以确定存储设备是否呈现旋转振动问题。执行工作负载分析以识别在物理上分开的硬件上运行的工作负载的变化，以解决旋转振动问题，从而消除对更昂贵的硬件的需要。

34. 发明授权

US08271140B2 Periodic rotational vibration check for storage devices to compensate for varying loads 有权
标题翻译：定期旋转振动检查存储设备，以补偿变化的负载
公开(公告)号：US08271140B2
公开(公告)日：2012-09-18
申请号：US11467417
申请日：2006-08-25
申请人： Brian James Cagno , Kenton Coleman Green , Carl Evan Jones , Michael Desmond O'Connell
发明人： Brian James Cagno , Kenton Coleman Green , Carl Evan Jones , Michael Desmond O'Connell
IPC分类号： G05D19/02 , G05B21/00
CPC分类号： G11B27/36 , G05B13/0205
摘要： A periodic rotational vibration check for storage devices to compensate for varying loads is disclosed. A variable representing rotational vibration status is maintained in a rotational vibration log. The variable is processed to determine whether a storage device exhibits a rotational vibration issue. Workload analysis is performed to identify a change to the workloads run on physically separate hardware to resolve the rotational vibration issue and thus eliminate the need for more expensive hardware.
摘要翻译：公开了用于存储装置的周期性旋转振动检查以补偿变化的负载。表示旋转振动状态的变量保持在旋转振动对数中。处理变量以确定存储设备是否呈现旋转振动问题。执行工作负载分析以识别在物理上分开的硬件上运行的工作负载的变化，以解决旋转振动问题，从而消除对更昂贵的硬件的需要。

35. 发明授权

US07536492B2 Apparatus, system, and method for automatically resetting an inter-integrated circuit bus 失效
标题翻译：用于自动复位集成电路总线的装置，系统和方法
公开(公告)号：US07536492B2
公开(公告)日：2009-05-19
申请号：US11626230
申请日：2007-01-23
申请人： Brian James Cagno , Kenny Nian Gau Qiu , Donald Scott Smith
发明人： Brian James Cagno , Kenny Nian Gau Qiu , Donald Scott Smith
IPC分类号： G06F13/00 , G06F13/14
CPC分类号： G06F13/4291
摘要： An apparatus, system, and method are disclosed for resetting an inter-integrated circuit (I2C) bus slave. A data line resistor in series is provided with a data line of an I2C bus in communication with the I2C bus slave. A clock line resistor in series is provided with a clock line of the I2C bus. A data line differential amplifier detects a first specified voltage across the data line resistor and a clock line differential amplifier detects a second specified voltage across the clock line resistor wherein the first specified voltage is substantially equal to a data line resistor resistance multiplied by a specified current and the second specified voltage is substantially equal to a clock line resistor resistance multiplied by the specified current. A time module detects the first and second specified voltage for a specified time interval. A reset module resets the I2C bus slave in response detecting the first and second specified voltage for the specified time interval.
摘要翻译：公开了用于复位集成电路（I2C）总线从设备的装置，系统和方法。串联的数据线电阻器具有与I2C总线从器件通信的I2C总线的数据线。串联的时钟线电阻器提供有I2C总线的时钟线。数据线差分放大器检测跨数据线电阻器的第一指定电压，并且时钟线差分放大器检测时钟线电阻器上的第二指定电压，其中第一指定电压基本上等于数据线电阻器乘以指定电流并且第二规定电压基本上等于与指定电流相乘的时钟线电阻器电阻。时间模块在指定的时间间隔内检测第一和第二指定电压。响应在指定时间间隔内检测到第一和第二指定电压，复位模块复位I2C总线从器件。

36. 发明授权

US07526589B2 Apparatus, system, and method for resetting an inter-integrated circuit data line using a negative voltage 失效
标题翻译：使用负电压复位集成电路数据线的装置，系统和方法
公开(公告)号：US07526589B2
公开(公告)日：2009-04-28
申请号：US11626227
申请日：2007-01-23
申请人： Brian James Cagno , Kenny Nian Gan Qiu , Donald Scott Smith
发明人： Brian James Cagno , Kenny Nian Gan Qiu , Donald Scott Smith
IPC分类号： G06F13/00 , G06F13/14
CPC分类号： G06F13/4295
摘要： An apparatus, system, and method are disclosed for resetting an inter-integrated circuit (I2C) data line with negative voltage. A hang detection module detects an I2C hung line selected from a data line and a clock line wherein an I2C bus master and I2C bus slave communicate over the data line and the clock line. In response to the detected hung line, a negative voltage generator drives the data line to a specified negative voltage for a specified time interval. A clamp diode clamps the voltage of the data line to greater than a specified limit. On receiving the specified negative voltage, a voltage detector module detects the specified negative voltage of the data line. A timer module detects the specified negative voltage for the specified time interval. In response to detecting the specified negative voltage for the specified time interval, a reset module resets the I2C bus slave.
摘要翻译：公开了一种用于重置具有负电压的集成电路（I2C）数据线的装置，系统和方法。挂起检测模块检测从数据线和时钟线选择的I2C挂起线，其中I2C总线主机和I2C总线从机通过数据线和时钟线进行通信。响应于检测到的悬挂线，负电压发生器以特定的时间间隔将数据线驱动到指定的负电压。钳位二极管将数据线的电压钳位到大于指定极限。在接收到指定的负电压时，电压检测器模块检测数据线的指定负电压。定时器模块在指定的时间间隔内检测指定的负电压。响应于在指定的时间间隔内检测到指定的负电压，复位模块将复位I2C总线从站。

37. 发明申请

US20080177916A1 APPARATUS, SYSTEM, AND METHOD FOR RESETTING AN INTER-INTEGRATED CIRCUIT DATA LINE USING A NEGATIVE VOLTAGE 失效
标题翻译：使用负电压复位内部集成电路数据线的装置，系统和方法
公开(公告)号：US20080177916A1
公开(公告)日：2008-07-24
申请号：US11626227
申请日：2007-01-23
申请人： Brian James Cagno , Kenny Nian Gan Qiu , Donald Scott Smith
发明人： Brian James Cagno , Kenny Nian Gan Qiu , Donald Scott Smith
IPC分类号： G06F13/00
CPC分类号： G06F13/4295
摘要： An apparatus, system, and method are disclosed for resetting an inter-integrated circuit (I2C) data line with negative voltage. A hang detection module detects an I2C hung line selected from a data line and a clock line wherein an I2C bus master and I2C bus slave communicate over the data line and the clock line. In response to the detected hung line, a negative voltage generator drives the data line to a specified negative voltage for a specified time interval. A clamp diode clamps the voltage of the data line to greater than a specified limit. On receiving the specified negative voltage, a voltage detector module detects the specified negative voltage of the data line. A timer module detects the specified negative voltage for the specified time interval. In response to detecting the specified negative voltage for the specified time interval, a reset module resets the I2C bus slave.
摘要翻译：公开了用于以负电压复位集成电路（I 2 C）数据线的装置，系统和方法。挂起检测模块检测从数据线和时钟线选择的I 2 C挂起线，其中I 2 C总线主机和I2C总线从机通过数据线和时钟线进行通信。响应于检测到的悬挂线，负电压发生器以特定的时间间隔将数据线驱动到指定的负电压。钳位二极管将数据线的电压钳位到大于指定极限。在接收到指定的负电压时，电压检测器模块检测数据线的指定负电压。定时器模块在指定的时间间隔内检测指定的负电压。响应于在指定的时间间隔内检测到指定的负电压，复位模块将复位I 2 C总线从站。

38. 发明授权

US08130084B2 Fault tolerant closed system control using power line communication 失效
标题翻译：使用电力线通信的容错闭路系统控制
公开(公告)号：US08130084B2
公开(公告)日：2012-03-06
申请号：US11742026
申请日：2007-04-30
申请人： Brian James Cagno , Kenny Nian Gan Qiu , Donald Scott Smith
发明人： Brian James Cagno , Kenny Nian Gan Qiu , Donald Scott Smith
IPC分类号： G05B11/01
CPC分类号： H04B3/544 , H04B1/74 , H04B2203/5458
摘要： A method, system, and computer program product are provided for communicating to a powered element in a rack system. A controller injects communication data onto power lines that provides power to a plurality of powered elements. The powered elements determine if the communication data transmitted via the power lines should be used for configuration using an address embedded within the communication data. The powered elements compare an embedded target address within the communication data to the address of the particular element. If there is a match between the addresses, the corresponding powered element processes the communication data to configure the powered element. As a result, data may be communicated over the power lines thereby eliminating the need for separate communication lines. Thus, the amount of cables required to interconnect the powered elements of the distributed data processing system may be reduced by eliminating the communication lines from the system configuration.
摘要翻译：提供了一种方法，系统和计算机程序产品，用于与机架系统中的有源元件进行通信。控制器将通信数据注入到向多个有源元件提供电力的电力线上。有源元件确定通过电力线传输的通信数据是否应使用嵌入在通信数据中的地址进行配置。有源元件将通信数据中的嵌入式目标地址与特定元素的地址进行比较。如果地址之间有匹配，则相应的有源元件处理通信数据以配置有源元件。因此，可以通过电力线传送数据，从而消除对单独通信线路的需要。因此，通过从系统配置中消除通信线路，可以减少互连分布式数据处理系统的供电元件所需的电缆量。

39. 发明授权

US07761728B2 Apparatus, system, and method for resetting an inter-integrated circuit data line with a clock line 失效
标题翻译：用时钟线复位集成电路数据线的装置，系统和方法
公开(公告)号：US07761728B2
公开(公告)日：2010-07-20
申请号：US11626220
申请日：2007-01-23
申请人： Brian James Cagno , Kenny Nian Gan Qiu , Donald Scott Smith
发明人： Brian James Cagno , Kenny Nian Gan Qiu , Donald Scott Smith
IPC分类号： G06F1/08
CPC分类号： G06F1/24
摘要： An apparatus, system, and method are disclosed for resetting an inter-integrated circuit data line with a clock line. A hang module detects that a data line that carries data between an I2C bus master and an I2C bus slave is hung, wherein the I2C bus master and I2C bus slave communicate over the data line and a clock line that carries a clock signal. The clock module increases a clock line frequency to a specified frequency in response to the detected data line hang. The pulse generation module transmits specified clock pulses from the I2C bus master to the I2C bus slave over the clock line at the specified increased frequency in response to the detected data line hang. A frequency detector module detects clock pulses at the specified increased frequency. A timer module detects the specified clock pulses at the specified increased frequency. A reset module resets the I2C bus slave in response detecting the specified clock pulses.
摘要翻译：公开了用时钟线重置集成电路数据线的装置，系统和方法。挂起模块检测到I2C总线主机和I2C总线从站之间携带数据的数据线是挂起的，其中I2C总线主机和I2C总线从站通过数据线通信，时钟线通过时钟信号进行通信。响应于检测到的数据线挂起，时钟模块将时钟线频率增加到指定频率。脉冲发生模块响应于检测到的数据线挂起，以指定的增加频率通过时钟线将指定的时钟脉冲从I2C总线主机传输到I2C总线从器件。频率检测器模块以指定的增加频率检测时钟脉冲。定时器模块以指定的增加频率检测指定的时钟脉冲。响应检测指定的时钟脉冲，复位模块复位I2C总线从器件。

40. 发明授权

US07661017B2 Diagnostic operations within a switched fibre channel arbitrated loop system 失效
标题翻译：交换光纤通道中的诊断操作仲裁环路系统
公开(公告)号：US07661017B2
公开(公告)日：2010-02-09
申请号：US11668879
申请日：2007-01-30
申请人： Donald Scott Smith , Brian James Cagno , Kenny Nian Gan Qiu
发明人： Donald Scott Smith , Brian James Cagno , Kenny Nian Gan Qiu
IPC分类号： G06F11/00
CPC分类号： G06F11/079 , G06F11/0727
摘要： Provided are a method, system, and article of manufacture wherein at least a first zone is maintained in a fibre channel arbitrated loop system, and wherein a plurality of storage devices is included in the first zone. A determination is made that diagnostic operations have to be performed on a storage device that is included in the plurality of storage devices. A second zone is generated, wherein the second zone includes the storage device on which the diagnostic operations have to be performed, and wherein the storage device is removed from the plurality of storage devices in the first zone leaving a remaining set of storage devices in the first zone. Diagnostic operations are performed on the storage device in the second zone while other operations are performed on the remaining set of storage devices in the first zone.
摘要翻译：提供了一种方法，系统和制品，其中至少第一区域保持在光纤通道仲裁环路系统中，并且其中多个存储设备包括在第一区域中。确定必须对包含在多个存储装置中的存储装置执行诊断操作。产生第二区域，其中第二区域包括其上必须执行诊断操作的存储设备，并且其中存储设备从第一区域中的多个存储设备中移除，留下剩余的存储设备组第一区。在第二区域中的存储设备上执行诊断操作，而对第一区域中的其余存储设备进行其它操作。

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