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31. 发明授权

US06912650B2 Pre-prefetching target of following branch instruction based on past history 失效
标题翻译：根据过去的历史预先预取跟随分支指令的目标
公开(公告)号：US06912650B2
公开(公告)日：2005-06-28
申请号：US09793559
申请日：2001-02-27
申请人： Masaki Ukai , Aiichiro Inoue
发明人： Masaki Ukai , Aiichiro Inoue
IPC分类号： G06F9/00 , G06F9/38
CPC分类号： G06F9/3804 , G06F9/3802
摘要： An instruction control apparatus, and method, used with a device including a cache memory, a lower memory, an instruction fetch device issuing an instruction fetch request for a target of a first branch instruction to the cache memory, and an instruction control device processing a instruction sequence stored in the cache memory. The apparatus and method pre-prefetch a target instruction sequence for a target of a second branch instruction. A predetermined instruction sequence based on a past history is preliminarily transferred from the lower memory to the cache memory when the target instruction sequence for the target of the first branch instruction is not in the cache memory.
摘要翻译：一种指令控制装置和方法，与包括高速缓冲存储器，下位存储器，向第一转移指令的指令取出请求发出到高速缓冲存储器的指令取出装置的装置一起使用，以及指令控制装置，存储在高速缓冲存储器中的指令序列。该装置和方法为第二分支指令的目标预预取目标指令序列。当第一分支指令的目标的目标指令序列不在高速缓冲存储器中时，基于过去历史的预定指令序列被预先从下部存储器传送到高速缓冲存储器。

32. 发明授权

US06606696B1 Virtual storage address space access control 失效
标题翻译：虚拟存储地址空间访问控制
公开(公告)号：US06606696B1
公开(公告)日：2003-08-12
申请号：US09461293
申请日：1999-12-15
申请人： Hiroshi Kawano , Aiichiro Inoue
发明人： Hiroshi Kawano , Aiichiro Inoue
IPC分类号： G06F1210
CPC分类号： G06F12/1036 , G06F12/109 , G06F12/1475
摘要： An AR map has entries of the same number as the AR's and is accessed by an ARN. In each of the map entries, there are entered: an ID of a pertinent entry in an STD array; and a flag representing valid or invalid of the map entry. Into an ALET holding part, there are stored ALET's corresponding to STD's in the STD array, respectively. Upon AR access, if an entry in the AR map which corresponds to a designated AR is valid, an ID included in the valid entry is outputted to a storage controlling part. In case that the corresponding entry in the AR map is invalid, if the ALET holding part stores an ALET identical with an ALET of the designated AR, an ID of STD corresponding to the stored ALET is stored into the AR map.
摘要翻译： AR地图具有与AR相同号码的条目，并由ARN访问。在每个地图条目中，输入：STD数组中相关条目的ID; 以及表示地图条目的有效或无效的标志。进入ALET保持部分，分别存储对应于STD数组中的STD的ALET。在AR访问中，如果对应于指定的AR的AR映射中的条目有效，则包含在有效条目中的ID被输出到存储控制部分。在AR映射对应的条目无效的情况下，如果ALET保持部分存储与指定AR的ALET相同的ALET，则与ARET对应的STD的ID被存储到AR映射中。

33. 发明授权

US5408620A Circuit for executing conditional branch instructions in pipeline process 失效
标题翻译：在流水线过程中执行条件分支指令的电路
公开(公告)号：US5408620A
公开(公告)日：1995-04-18
申请号：US828701
申请日：1992-01-31
申请人： Takeo Asakawa , Aiichiro Inoue
发明人： Takeo Asakawa , Aiichiro Inoue
IPC分类号： G06F9/32 , G06F9/38
CPC分类号： G06F9/30094 , G06F9/3844
摘要： A circuit for executing conditional branch instructions in a pipeline process comprises registers for retaining condition codes settled set or determined at different stages, respectively, registers for retaining pipeline tags identifying instructions at the respective stages and indicating the stage where the condition codes are settled or set by the instructions, and a branch controller for deciding whether the settlement of condition codes for conditional branch instructions existing at the respective stage has occured responsive to the tags in a plurality of stages, and for selecting the settled condition codes from among the condition codes stored in the registers and indicating whether a branch should be performed.
摘要翻译：用于在流水线处理中执行条件分支指令的电路分别包括用于保存在不同阶段设置或确定的条件代码的寄存器，用于保留在各个阶段识别指令的流水线标签的寄存器，并且指示状态代码被结算或设置的阶段以及分支控制器，用于判定是否已经发生存在于各个阶段的条件转移指令的条件码的结算，以响应于多个级中的标签，并且从存储的条件代码中选择确定的条件代码在寄存器中并指示是否应该执行分支。

34. 发明授权

US4852021A Centralized command transfer control system for connecting processors which independently send and receive commands 失效
标题翻译：用于连接独立发送和接收命令的处理器的集中式命令传输控制系统
公开(公告)号：US4852021A
公开(公告)日：1989-07-25
申请号：US198659
申请日：1988-05-19
申请人： Aiichiro Inoue , Katsumi Onishi , Yuji Oinaga , Kenichi Nojima
发明人： Aiichiro Inoue , Katsumi Onishi , Yuji Oinaga , Kenichi Nojima
IPC分类号： G06F15/16 , G06F13/00 , G06F15/17 , G06F15/173
CPC分类号： G06F15/17
摘要： A system for controlling the transfer of commands between processors of a multiprocessor system, including a single control unit connected to all the processors by separate information transfer lines. The control unit selects the processor generating a command transfer request signal in a predetermined priority order and receives the processor address from the selected processor. The receiving processor and predetermined transfer information are determined in accordance with the selected processor, the processor address, and the processor status information determined by the processor address. The predetermined transfer information is transferred to the receiving processor via an information transfer path established between the selected processor and the receiving processor.
摘要翻译：一种用于控制多处理器系统的处理器之间的命令传送的系统，包括通过单独的信息传输线连接到所有处理器的单个控制单元。控制单元选择处理器以预定优先级顺序生成命令传送请求信号，并从所选择的处理器接收处理器地址。根据所选择的处理器，处理器地址和由处理器地址确定的处理器状态信息确定接收处理器和预定传送信息。预定的传送信息经由在所选择的处理器和接收处理器之间建立的信息传送路径传送到接收处理器。

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