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31. 发明申请

US20070134871A1 Memory chip having a memory cell with low-temperature layers in the memory trench and fabrication method 审中-公开
标题翻译：存储芯片具有存储槽中具有低温层的存储单元和制造方法
公开(公告)号：US20070134871A1
公开(公告)日：2007-06-14
申请号：US11702162
申请日：2007-02-05
申请人： Dietmar Temmler , Martin Gutsche , Martin Popp , Harald Seidl
发明人： Dietmar Temmler , Martin Gutsche , Martin Popp , Harald Seidl
IPC分类号： H01L21/8242
CPC分类号： H01L27/10867 , H01L27/10832 , H01L27/10864
摘要： Memory cells having trench capacitors, the trench capacitor being at least partially filled with a material which could not withstand high-temperature processes used during the fabrication of a memory chip without impairment of its electrical parameters. What is essential to the invention is that the material of the trench capacitor is introduced into the trench after the high-temperature processes. The method according to the invention makes it possible to use dielectric layers having large dielectric constants and electrode layers made of metallic material. The electrical properties of the trench capacitor are thus improved in comparison with known trench capacitors.
摘要翻译：具有沟槽电容器的存储单元，沟槽电容器至少部分地填充有不能承受在制造存储器芯片期间使用的高温处理而不损害其电参数的材料。本发明的重要内容是在高温处理之后将沟槽电容器的材料引入沟槽。根据本发明的方法使得可以使用具有大介电常数的电介质层和由金属材料制成的电极层。与已知的沟槽电容器相比，沟槽电容器的电性能得到改善。

32. 发明授权

US07157371B2 Barrier layer and a method for suppressing diffusion processes during the production of semiconductor devices 有权
标题翻译：阻挡层以及在制造半导体器件期间抑制扩散过程的方法
公开(公告)号：US07157371B2
公开(公告)日：2007-01-02
申请号：US10653599
申请日：2003-09-02
申请人： Thomas Hecht , Uwe Schroeder , Harald Seidl , Martin Gutsche , Stefan Jakschik , Stephan Kudelka , Albert Birner
发明人： Thomas Hecht , Uwe Schroeder , Harald Seidl , Martin Gutsche , Stefan Jakschik , Stephan Kudelka , Albert Birner
IPC分类号： H01L21/44
CPC分类号： H01L27/11502 , H01L21/02178 , H01L21/02181 , H01L21/28061 , H01L21/31138 , H01L21/31604 , H01L21/3162 , H01L21/76802 , H01L21/76828 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L27/11507 , H01L28/57 , H01L29/0895 , H01L29/4941
摘要： A dielectric barrier layer composed of a metal oxide is applied in thin layers with a thickness of less than 20 nanometers in the course of processing semiconductor devices by sequential gas phase deposition or molecular beam epitaxy in molecular individual layers on differently structured base substrates. The method allows, inter alias, effective conductive diffusion barriers to be formed from a dielectric material, an optimization of the layer thickness of the barrier layer, an increase in the temperature budget for subsequent process steps, and a reduction in the effort for removing the temporary barrier layers.
摘要翻译：由金属氧化物构成的电介质阻挡层通过在不同结构的基底衬底上的分子单层中的顺序气相沉积或分子束外延处理半导体器件的过程中以小于20纳米的厚度施加。该方法允许间隔地从电介质材料形成有效的导电扩散阻挡层，优化阻挡层的层厚度，随后的工艺步骤的温度预算的增加以及用于去除临时阻隔层。

33. 发明授权

US07074689B2 Method for fabricating a trench capacitor having an insulation collar, which is electrically connected to a substrate on one side via a buried contact, in particular for a semiconductor memory cell 失效
标题翻译：一种用于制造具有绝缘套环的沟槽电容器的方法，所述绝缘套环通过埋入触点电连接到一侧的衬底，特别是用于半导体存储器单元
公开(公告)号：US07074689B2
公开(公告)日：2006-07-11
申请号：US10935520
申请日：2004-09-07
申请人： Martin Gutsche , Harald Seidl
发明人： Martin Gutsche , Harald Seidl
IPC分类号： H01L21/20
CPC分类号： H01L27/10867 , H01L27/10829 , H01L27/1087 , H01L29/66181
摘要： The present invention provides a method for fabricating a trench capacitor having an insulation collar (10; 10a, 10b) in a substrate (1), which is electrically connected to the substrate (1) on one side via a buried contact (15a, 15b), in particular for a semiconductor memory cell having a planar select transistor which is provided in the substrate (1) and is connected via the buried contact (15a, 15b), comprising the steps of: providing a trench (5) in the substrate (1) using a hard mask (2, 3) with a corresponding mask opening; providing a capacitor dielectric (30) in the lower and middle regions of the trench, the insulation collar (10) in the middle and upper regions of the trench and an electrically conductive filling (20) at least up to the top side of the insulation collar (10); completely filling the trench (5) with a filling material (50; 50′; 50″; 20); carrying out an STI trench production process; removing the filling material (50; 50′; 50″; 20) and lowering the electrically conductive filling (20) to below the top side of the insulation collar (10); forming an insulation region (IS; IS1, IS2) on one side with respect to the substrate (1) above the insulation collar (10); uncovering a connection region (KS; KS1, KS2) on the other side with respect to the substrate (1) above the insulation collar (10); and forming the buried contact (15a, 15b) by depositing and etching back a C filling (70; 70′; 70″; 70′″).
摘要翻译：本发明提供一种用于制造在衬底（1）中具有绝缘套环（10; 10a，10b）的沟槽电容器的方法，所述衬底（1）通过埋入触点（15）电连接到衬底（1） a）15b），特别是具有设置在基板（1）中并通过埋入触点（15a，15b）连接的平面选择晶体管的半导体存储单元，包括以下步骤：提供沟槽（5）在使用具有对应的掩模开口的硬掩模（2,3）的基板（1）中; 在所述沟槽的下部和中部区域中提供电容器电介质（30），所述沟槽的中部和上部区域中的所述绝缘环（10）和至少直到所述绝缘体的顶侧的导电填料（20）衣领（10）; 用填充材料（50; 50'; 50“; 20）完全填充沟槽（5）; 开展STI沟槽生产工艺; 去除所述填充材料（50; 50'; 50“; 20）并将所述导电填料（20）降低到所述绝缘套环（10）的顶侧下方; 在所述绝缘套环（10）上方相对于所述衬底（1）在一侧上形成绝缘区域（IS; IS 1，IS 2）; 相对于绝缘套环（10）上方的基板（1）露出另一侧的连接区域（KS; KS 1，KS 2）; 以及通过沉积和蚀刻C填充物（70; 70'; 70“，70”'）来形成所述埋入触点（15a，15b）。

34. 发明申请

US20060125108A1 Method of producing a microelectronic electrode structure, and microelectronic electrode structure 有权
标题翻译：微电子电极结构的制造方法和微电子电极结构
公开(公告)号：US20060125108A1
公开(公告)日：2006-06-15
申请号：US11296740
申请日：2005-12-07
申请人： Martin Gutsche , Harald Seidl
发明人： Martin Gutsche , Harald Seidl
IPC分类号： H01L23/48
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： In a method for producing a microelectronic electrode structure a first wiring plane is prepared, an insulating region on the first wiring plane is provided, a through-hole in the insulating region is formed, a ring electrode in the through-hole is formed, and a second wiring plane is formed on the insulating region. The ring electrode comprises a first side and a second side, the ring electrode is electrically connected on the first side to the first wiring plane, and the second wiring plane is electrically connected to the second side of the ring electrode.
摘要翻译：在制造微电子电极结构体的方法中，制备第一布线面，设置第一布线面上的绝缘区域，形成绝缘区域的贯通孔，形成通孔内的环状电极，在绝缘区域上形成第二布线平面。环形电极包括第一侧和第二侧，环形电极在第一侧电连接到第一布线平面，并且第二布线平面电连接到环形电极的第二侧。

35. 发明申请

US20060019447A1 Process for the self-aligning production of a transistor with a U-shaped gate 审中-公开
标题翻译：用于U型栅极的晶体管的自对准生产工艺
公开(公告)号：US20060019447A1
公开(公告)日：2006-01-26
申请号：US11185584
申请日：2005-07-20
申请人： Martin Gutsche , Harald Seidl
发明人： Martin Gutsche , Harald Seidl
IPC分类号： H01L21/336 , H01L21/338
CPC分类号： H01L29/66621 , H01L21/823412 , H01L21/823437 , H01L27/10876 , H01L29/4236 , H01L29/42376 , H01L29/66545 , H01L29/7834
摘要： The present invention provides a process for producing a gate element for a transistor, in which a substrate (101) is provided, an insulation layer (104) and a sacrificial layer (105) are deposited on the substrate (101), the sacrificial layer (105) is patterned and a spacing layer (107) is deposited on the sacrificial layer, the spaces in the patterned sacrificial layer (105) are filled with a filling layer (108), the sacrificial layer structure (105a, 105b) and regions of the insulation layer (104) which are located beneath the sacrificial layer structure (105a, 105b) are removed. Finally, recesses (110) are etched into the substrate (101), the spacing layer (107) and those regions of the insulation layer which are not covered by the filling layer (108) are removed, a gate oxide layer (111) of the gate element is deposited and a gate electrode layer (112) of the gate element is deposited in the recesses (110). After the filling layer (108) has been removed, the result is a gate element for a field effect transistor with a low leakage current which can advantageously be used as a select transistor for a memory cell of a memory cell array.
摘要翻译：本发明提供了一种用于制造晶体管的栅极元件的方法，其中提供衬底（101），在衬底（101）上沉积绝缘层（104）和牺牲层（105），牺牲层（105）被图案化并且在牺牲层上沉积间隔层（107），图案化牺牲层（105）中的空间填充有填充层（108），牺牲层结构（105a，105b）并且去除位于牺牲层结构（105a，105b）下方的绝缘层（104）的区域。最后，将凹槽（110）蚀刻到衬底（101）中，去除间隔层（107）和未被填充层（108）覆盖的绝缘层的那些区域，去除栅极氧化物层（111）沉积栅极元件，并且栅极元件的栅电极层（112）沉积在凹槽（110）中。在填充层（108）已经被去除之后，结果是用于具有低泄漏电流的场效应晶体管的栅极元件，其可以有利地用作存储器单元阵列的存储器单元的选择晶体管。

36. 发明申请

US20060001067A1 Fabrication method for a semiconductor structure having integrated capacitors and corresponding semicomductor structure 有权
标题翻译：具有集成电容器和相应半导体结构的半导体结构的制造方法
公开(公告)号：US20060001067A1
公开(公告)日：2006-01-05
申请号：US11127505
申请日：2005-05-12
申请人： Martin Gutsche , Harald Seidl
发明人： Martin Gutsche , Harald Seidl
IPC分类号： H01L29/00 , H01L21/20
CPC分类号： H01L28/92 , H01L27/0805 , H01L27/1087 , H01L28/91 , H01L29/66181 , H01L29/945
摘要： The present invention provides a fabrication method for a semiconductor structure having integrated capacitors and a corresponding semiconductor structure. The fabrication method has the following steps of: providing a semiconductor substrate (1; 1′, 60, 1″) having a front side (VS) and a rear side (RS); providing trenches (5) in the semiconductor substrate (1; 1′, 60, 1″) proceeding from the front side (VS) of the semiconductor substrate (1; 1′, 60, 1″); providing a respective inner capacitor electrode (6) in the trenches (5); uncovering the inner capacitor electrodes (6) proceeding from the rear side (RS) of the semiconductor substrate (1; 1′, 60, 1″); providing a capacitor dielectric (40) on the uncovered inner capacitor electrodes (6); and providing outer capacitor electrodes (50) on the capacitor dielectric (40) on the inner capacitor electrodes (6).
摘要翻译：本发明提供一种具有集成电容器和相应的半导体结构的半导体结构的制造方法。该制造方法具有以下步骤：提供具有前侧（VS）和后侧（RS）的半导体衬底（1; 1'，60“1”）; 在半导体衬底（1; 1'，60“1”）的前侧（VS）上提供在半导体衬底（1; 1'，60“1”）中的沟槽（5）在沟槽（5）中提供相应的内部电容器电极（6）; 露出从半导体衬底（1; 1'，60,1“）的后侧（RS）延伸的内部电容器电极（6）; 在未覆盖的内部电容器电极（6）上提供电容器电介质（40）; 以及在内部电容器电极（6）上的电容器电介质（40）上提供外部电容器电极（50）。

37. 发明授权

US06953722B2 Method for patterning ceramic layers 失效
标题翻译：图案化陶瓷层的方法
公开(公告)号：US06953722B2
公开(公告)日：2005-10-11
申请号：US10425461
申请日：2003-04-29
申请人： Harald Seidl , Martin Gutsche , Thomas Hecht , Stefan Jakschik , Stephan Kudelka , Uwe Schröder , Matthias Schmeide
发明人： Harald Seidl , Martin Gutsche , Thomas Hecht , Stefan Jakschik , Stephan Kudelka , Uwe Schröder , Matthias Schmeide
IPC分类号： H01L21/311 , H01L21/8242
CPC分类号： H01L27/10867 , H01L21/31133
摘要： In a method for forming patterned ceramic layers, a ceramic material is deposited on a substrate and is subsequently densified by heat treatment, for example. In this case, the initially amorphous material is converted into a crystalline or polycrystalline form. In order that the now crystalline material can be removed again from the substrate, imperfections are produced in the ceramic material, for example by ion implantation. As a result, the etching medium can more easily attack the ceramic material, so that the latter can be removed with a higher etching rate. Through inclined implantation, the method can be performed in a self-aligning manner and the ceramic material can be removed on one side, by way of example, in trenches or deep trench capacitors.
摘要翻译：在用于形成图案化陶瓷层的方法中，陶瓷材料沉积在基底上，并随后通过热处理致密化。在这种情况下，最初的无定形材料被转化为结晶或多晶形式。为了现在的结晶材料可以再次从衬底去除，例如通过离子注入在陶瓷材料中产生缺陷。结果，蚀刻介质可以更容易地侵蚀陶瓷材料，使得后者可以以更高的蚀刻速率被去除。通过倾斜注入，该方法可以以自对准的方式进行，并且陶瓷材料可以通过例如在沟槽或深沟槽电容器中被一侧除去。

38. 发明申请

US20050191806A1 Method for fabricating a memory cell 有权
标题翻译：用于制造存储单元的方法
公开(公告)号：US20050191806A1
公开(公告)日：2005-09-01
申请号：US11055431
申请日：2005-02-10
申请人： Martin Gutsche , Harald Seidl
发明人： Martin Gutsche , Harald Seidl
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/94 , H01L31/119
CPC分类号： H01L27/1087
摘要： The invention provides a method for fabricating a memory cell for storing electric charge, which has a substrate (101), which forms a first electrode, a trench-like recess (102) etched into the substrate (101), conductive material, which is provided as a projection in a central region of the trench-like recess (102) and spaced apart from the side walls (107) of the trench-like recess (102) and is in electrical contact with the substrate at the base (104) of the trench-like recess (102), a dielectric layer (108), which has been deposited on the side walls (107) of the trench-like recess (102), the base (104) of the trench-like recess (102) and the surfaces of the conductive material (105), and an electrode layer (110), which has been deposited on the dielectric layer (108) and forms a second electrode.
摘要翻译：本发明提供了一种用于制造用于存储电荷的存储单元的方法，该方法具有形成第一电极的基板（101），蚀刻到基板（101）中的沟槽状凹部（102），导电材料设置为在所述沟槽状凹部（102）的中心区域中并与所述沟槽状凹部（102）的侧壁（107）间隔开并且与所述基底（104）处的所述基板电接触的突起，已经沉积在沟槽状凹部（102）的侧壁（107）上的电介质层（108），沟槽状凹部（102）的基底（104） 102）和导电材料（105）的表面以及已经沉积在电介质层（108）上并形成第二电极的电极层（110）。

39. 发明申请

US20050095780A1 Method for fabricating memory cells and memory cell array 失效
标题翻译：用于制造存储单元和存储单元阵列的方法
公开(公告)号：US20050095780A1
公开(公告)日：2005-05-05
申请号：US10952371
申请日：2004-09-29
申请人： Martin Gutsche , Franz Kreupl
发明人： Martin Gutsche , Franz Kreupl
IPC分类号： H01L21/02 , H01L21/314 , H01L21/316 , H01L21/8242 , H01L21/8234
CPC分类号： H01L27/1087 , H01L21/3141 , H01L21/31645 , H01L28/91
摘要： A method for producing memory cells, in which an electrically conductive substrate is provided, a trench structure or cup structure with side walls and a base is formed in or on the substrate, a first insulation layer is deposited at the side walls, a capacitor material is deposited on the base, a nanostructure is grown starting from and electrically connected to the catalyst material deposited on the base, a second insulation layer is deposited on the nanostructure and on the base, and finally an electrically conductive layer is deposited as a counterelectrode on the first insulation layer and second insulation layer.
摘要翻译：一种制造存储单元的方法，其中提供导电基底，在基底中或基底上形成具有侧壁和基底的沟槽结构或杯结构，在侧壁上沉积第一绝缘层，电容器材料沉积在基底上，从沉积在基底上的催化剂材料开始生长和电连接纳米结构，在纳米结构和基底上沉积第二绝缘层，最后作为反电极沉积导电层第一绝缘层和第二绝缘层。

40. 发明授权

US06207584B1 High dielectric constant material deposition to achieve high capacitance 有权
标题翻译：高介电常数材料沉积实现高电容
公开(公告)号：US06207584B1
公开(公告)日：2001-03-27
申请号：US09478270
申请日：2000-01-05
申请人： Hua Shen , David E. Kotecki , Robert Laibowitz , Katherine Lynn Saenger , Satish D. Athavale , Jenny Lian , Martin Gutsche , Yun-Yu Wang , Thomas Shaw
发明人： Hua Shen , David E. Kotecki , Robert Laibowitz , Katherine Lynn Saenger , Satish D. Athavale , Jenny Lian , Martin Gutsche , Yun-Yu Wang , Thomas Shaw
IPC分类号： H01L2131
CPC分类号： H01L28/56 , H01L21/31691 , H01L28/90
摘要： A method for forming a dielectric layer includes exposing a surface to a first dielectric material in gaseous form at a first temperature. Nuclei of the first dielectric material are formed on the surface. A layer of a second dielectric material is deposited on the surface by employing the nuclei as seeds for layer growth wherein the depositing is performed at a second temperature which is greater than the first temperature.
摘要翻译：形成电介质层的方法包括在第一温度下将表面暴露于气态的第一电介质材料。在表面上形成第一介电材料的核。通过使用核作为种子用于层生长，在表面上沉积第二介电材料层，其中沉积在大于第一温度的第二温度下进行。

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