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31. 发明申请

US20150014929A1 Solitaire peg jumping game 审中-公开
标题翻译：接龙钉跳跃游戏
公开(公告)号：US20150014929A1
公开(公告)日：2015-01-15
申请号：US14326063
申请日：2014-07-08
申请人： Mark Bauer
发明人： Mark Bauer
IPC分类号： A63F3/00
CPC分类号： A63F9/0602 , A63F3/02 , A63F2003/00195 , A63F2003/00593 , A63F2003/00949
摘要： A game device which is used to play a solitaire peg jumping game, and a method of playing the game, functions by requiring the user to jump pegs, where the jumped pegs are removed, and the user continues jumping until one peg remains. The design is in a particular hexagonal shape, which can be produced in a travel size to support portability for traveling.
摘要翻译：用于播放纸牌跳跃游戏的游戏装置，以及玩游戏的方法，通过要求用户跳过钉，其中跳过的钉被移除，并且用户继续跳跃直到一个钉留下来起作用。该设计是特定的六边形形状，其可以以旅行尺寸生产以支持行驶的便携性。

32. 发明授权

US08482979B2 Data path for multi-level cell memory, methods for storing and methods for utilizing a memory array 有权
标题翻译：用于多级单元存储器的数据路径，存储方法和利用存储器阵列的方法
公开(公告)号：US08482979B2
公开(公告)日：2013-07-09
申请号：US13431837
申请日：2012-03-27
申请人： Mark Bauer
发明人： Mark Bauer
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/56 , G11C11/5628 , G11C11/5642 , G11C16/06 , G11C2211/5641
摘要： Memories, data paths, methods for storing, and methods for utilizing are disclosed, including a data path for a memory using multi-level memory cells to provide storage of multiple bits per memory cell. One such data path includes a bit mapping circuit and a data converter circuit. Such a bit mapping circuit can be configured to map bits of the original data to an intermediate arrangement of bits and such a data converter circuit can be configured to receive the intermediate arrangement of bits and convert the intermediate arrangement of bits into intermediate data corresponding to a memory state to be stored by memory cells of a memory cell array.
摘要翻译：公开了存储器，数据路径，存储方法和利用方法，包括使用多级存储单元的存储器的数据路径，以提供每存储器单元多位的存储。一个这样的数据路径包括位映射电路和数据转换器电路。这样的位映射电路可以被配置为将原始数据的位映射到位的中间排列，并且这样的数据转换器电路可以被配置为接收位的中间排列，并将位的中间排列转换成对应于由存储单元阵列的存储单元存储的存储器状态。

33. 发明授权

US08374027B2 Data path for multi-level cell memory, methods for storing and methods for utilizing a memory array 有权
公开(公告)号：US08374027B2
公开(公告)日：2013-02-12
申请号：US12956977
申请日：2010-11-30
申请人： Mark Bauer
发明人： Mark Bauer
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/56 , G11C11/5628 , G11C11/5642 , G11C16/06 , G11C2211/5641
摘要： Memories, data paths, methods for storing, and methods for utilizing are disclosed, including a data path for a memory using multi-level memory cells to provide storage of multiple bits per memory cell. One such data path includes a bit mapping circuit and a data converter circuit. Such a bit mapping circuit can be configured to map bits of the original data to an intermediate arrangement of bits and such a data converter circuit can be configured to receive the intermediate arrangement of bits and convert the intermediate arrangement of bits into intermediate data corresponding to a memory state to be stored by memory cells of a memory cell array.

34. 发明申请

US20100210716A1 Process for Preparing an Alpha-Lipoic Acid/Cyclodextrin Complex and Product Prepared 有权
标题翻译：制备α-硫辛酸/环糊精复合物的方法和制备的产物
公开(公告)号：US20100210716A1
公开(公告)日：2010-08-19
申请号：US12768976
申请日：2010-04-28
申请人： Helmut Reuscher , Mark Bauer
发明人： Helmut Reuscher , Mark Bauer
IPC分类号： A61K31/385 , A61P3/10 , A61P1/16 , A61P5/50
CPC分类号： A61K31/385 , A61K31/724 , A61K47/6951 , B82Y5/00
摘要： The invention relates to a process for the preparation of a cyclodextrin/alpha-lipoic acid complex, wherein in a first step, an alpha-lipoic acid and a cyclodextrin are dissolved in an aqueous alkaline solution having a pH above pH 7, and in a second step an acid is added to lower the pH of the solution to a pH below pH 7.
摘要翻译：本发明涉及一种制备环糊精/α-硫辛酸络合物的方法，其中在第一步中将α-硫辛酸和环糊精溶于pH高于pH 7的碱性水溶液中，第二步，加入酸以将溶液的pH降至低于pH 7的pH。

35. 发明申请

US20100110788A1 DATA PATH FOR MULTI-LEVEL CELL MEMORY, METHODS FOR STORING AND METHODS FOR UTILIZING A MEMORY ARRAY 有权
标题翻译：用于多级细胞存储器的数据路径，用于存储的方法和使用存储器阵列的方法
公开(公告)号：US20100110788A1
公开(公告)日：2010-05-06
申请号：US12261928
申请日：2008-10-30
申请人： Mark Bauer
发明人： Mark Bauer
IPC分类号： G11C16/00 , G11C7/00 , G11C16/06
CPC分类号： G11C16/10 , G11C11/56 , G11C11/5628 , G11C11/5642 , G11C16/06 , G11C2211/5641
摘要： Memories, data paths, methods for storing, and methods for utilizing are disclosed, including a data path for a memory using multi-level memory cells to provide storage of multiple bits per memory cell. One such data path includes a bit mapping circuit and a data converter circuit. Such a bit mapping circuit can be configured to map bits of the original data to an intermediate arrangement of bits and such a data converter circuit can be configured to receive the intermediate arrangement of bits and convert the intermediate arrangement of bits into intermediate data corresponding to a memory state to be stored by memory cells of a memory cell array.
摘要翻译：公开了存储器，数据路径，存储方法和利用方法，包括使用多级存储单元的存储器的数据路径，以提供每存储器单元多位的存储。一个这样的数据路径包括位映射电路和数据转换器电路。这样的位映射电路可以被配置为将原始数据的位映射到位的中间排列，并且这样的数据转换器电路可以被配置为接收位的中间排列，并将位的中间排列转换成对应于由存储单元阵列的存储单元存储的存储器状态。

36. 发明授权

US07583559B2 Two transistor wordline decoder output driver 失效
标题翻译：两个晶体管字线解码器输出驱动
公开(公告)号：US07583559B2
公开(公告)日：2009-09-01
申请号：US11756419
申请日：2007-05-31
申请人： Hari Giduturi , Mark Bauer , Hernan A. Castro
发明人： Hari Giduturi , Mark Bauer , Hernan A. Castro
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/12
摘要： A wordline decoder scheme for a memory device is generally described. In one example, a memory device includes a distributed logical NOR gate to decode addressing signals to generate wordline selection signals within a block of memory wherein the distributed logical NOR gate comprises a wordline decoder output driver, the wordline decoder output driver comprising two transistors coupled with a wordline signal.
摘要翻译：通常描述用于存储器件的字线解码器方案。在一个示例中，存储器件包括分布式逻辑“或”门，用于解码寻址信号以在存储器块内产生字线选择信号，其中分布逻辑或非门包括字线解码器输出驱动器，字线解码器输出驱动器包括与字线信号。

37. 发明授权

US5444656A Apparatus for fast internal reference cell trimming 失效
标题翻译：用于快速内部参考细胞修剪的装置
公开(公告)号：US5444656A
公开(公告)日：1995-08-22
申请号：US252908
申请日：1994-06-02
申请人： Mark Bauer , Johnny Javanifard
发明人： Mark Bauer , Johnny Javanifard
IPC分类号： G11C7/14 , G11C11/56 , G11C16/28 , G11C11/40
CPC分类号： G11C11/5621 , G11C11/5642 , G11C16/28 , G11C7/14 , G11C2211/5634
摘要： A memory array having memory devices arranged in rows and columns, each column including a load device across which a first voltage level is provided when a memory device being read is in one condition and a second voltage level is provided when a memory device being read is in a second condition, a reference device arranged in series with another load device, a sensing device for detecting the voltages across the load devices and providing a first output signal when the voltage across the first load device is greater than the voltage across the second voltage device and a second output when the voltage across the first load device is less than the voltage across the second voltage device. The array also includes an arrangement for decoupling the memory devices and the associated load devices and applying a precise voltage equivalent to the one of the voltages across the load device while programming the reference devices so that the voltage across the second load device is compared to this precise voltage when the reference device is being programmed.
摘要翻译：一种具有排列成行和列的存储器件的存储器阵列，每列包括负载装置，当正被读取的存储器件处于一个状态时，该负载装置提供第一电压电平，并且当正被读取的存储器件被提供时提供第二电压电平在第二状态下，与另一负载装置串联布置的参考装置，用于检测跨越负载装置的电压的感测装置，并且当第一负载装置两端的电压大于第二电压两端的电压时，提供第一输出信号当所述第一负载装置两端的电压小于所述第二电压装置两端的电压时，所述装置和所述第二输出端。该阵列还包括用于对存储器件和相关联的负载器件进行去耦的装置，并在对参考器件进行编程的同时施加等效于负载器件中的一个电压的精确电压，从而将第二负载器件上的电压与此相比较参考设备编程时的精确电压。

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