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31. 发明授权

US06762114B1 Methods for transistor gate fabrication and for reducing high-k gate dielectric roughness 有权
标题翻译：晶体管栅极制造方法和降低高k栅介质粗糙度的方法
公开(公告)号：US06762114B1
公开(公告)日：2004-07-13
申请号：US10335557
申请日：2002-12-31
申请人： James Joseph Chambers
发明人： James Joseph Chambers
IPC分类号： H01L213205
CPC分类号： H01L29/513 , H01L21/28167 , H01L21/28194 , H01L21/28202 , H01L29/517 , H01L29/518
摘要： Methods are disclosed for fabricating transistor gate structures in which high-k dielectric layer roughness is reduced by formation of a nucleation promotion layer over the substrate or any intentional interface layers, and a high-k gate dielectric is formed over the nucleation promotion layer. The nucleation promotion layer has a thickness of 10 Å or less, such as a monolayer or a sub-monolayer, comprising a metal, a metal silicide, or a metal silicate, which promotes uniform chemical vapor deposition of high-k gate dielectric materials by increasing the density of nucleation sites on the substrate or intentional interface layer.
摘要翻译：公开了用于制造晶体管栅极结构的方法，其中通过在衬底或任何有意界面层上形成成核促进层来降低高k介电层粗糙度，并且在成核促进层上形成高k栅极电介质。成核促进层的厚度为10μm以下，例如单层或亚单层，其包含金属，金属硅化物或金属硅酸盐，其促进高k栅极电介质材料的均匀化学气相沉积增加基底或有意界面层上的成核位点的密度。

32. 发明授权

US08536654B2 Structure and method for dual work function metal gate CMOS with selective capping 有权
标题翻译：具有选择性封盖的双功能金属栅极CMOS的结构和方法
公开(公告)号：US08536654B2
公开(公告)日：2013-09-17
申请号：US13006185
申请日：2011-01-13
申请人： James Joseph Chambers , Hiroaki Niimi
发明人： James Joseph Chambers , Hiroaki Niimi
IPC分类号： H01L29/76
CPC分类号： H01L21/283 , H01L21/28079 , H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/66545
摘要： A CMOS device having an NMOS transistor with a metal gate electrode comprising a mid-gap metal with a low work function/high oxygen affinity cap and a PMOS transistor with a metal gate electrode comprising a mid gap metal with a high work function/low oxygen affinity cap and method of forming.
摘要翻译：一种具有NMOS晶体管的CMOS器件，其具有包括具有低功函数/高氧亲和性帽的中间间隙金属的金属栅极和具有金属栅电极的PMOS晶体管，该金属栅电极包括具有高功函数/低氧的中间间隙金属亲和帽和成型方法。

33. 发明授权

US08450221B2 Method of forming MOS transistors including SiON gate dielectric with enhanced nitrogen concentration at its sidewalls 有权
标题翻译：包括在其侧壁具有增强的氮浓度的SiON栅极电介质的MOS晶体管的方法
公开(公告)号：US08450221B2
公开(公告)日：2013-05-28
申请号：US12850097
申请日：2010-08-04
申请人： Brian K. Kirkpatrick , James Joseph Chambers
发明人： Brian K. Kirkpatrick , James Joseph Chambers
IPC分类号： H01L21/00
CPC分类号： H01L29/518 , H01L21/28044 , H01L21/28202 , H01L29/78
摘要： A method of forming an integrated circuit (IC) having at least one MOS device includes forming a SiON gate dielectric layer on a silicon surface. A gate electrode layer is deposited on the SiON gate layer and then patterning forms a gate stack. Exposed gate dielectric sidewalls are revealed by the patterning. A supplemental silicon oxide layer is formed on the exposed SiON sidewalls followed by nitriding. After nitriding, a post nitridation annealing (PNA) forms an annealed N-enhanced SiON gate dielectric layer including N-enhanced SiON sidewalls, wherein along lines of constant thickness a N concentration at the N-enhanced SiON sidewalls is ≧ the N concentration in a bulk of the annealed N-enhanced SiON gate layer −2 atomic %. A source and drain region on opposing sides of the gate stack are formed to define a channel region under the gate stack.
摘要翻译：形成具有至少一个MOS器件的集成电路（IC）的方法包括在硅表面上形成SiON栅介质层。在SiON栅极层上沉积栅电极层，然后构图形成栅叠层。通过图案化揭示了暴露的栅极电介质侧壁。在暴露的SiON侧壁上形成补充的氧化硅层，然后氮化。氮化后，氮化退火（PNA）形成包括N增强SiON侧壁的退火的N增强SiON栅极电介质层，其中沿着恒定厚度的线，N增强SiON侧壁处的N浓度> 大部分退火的N增强SiON栅极层-2原子％。形成栅极堆叠的相对侧上的源极和漏极区域以限定栅极叠层下方的沟道区域。

34. 发明授权

US08441078B2 Semiconductor device including SiON gate dielectric with portions having different nitrogen concentrations 有权
标题翻译：包括具有不同氮浓度的部分的SiON栅极电介质的半导体器件
公开(公告)号：US08441078B2
公开(公告)日：2013-05-14
申请号：US12710709
申请日：2010-02-23
申请人： James Joseph Chambers , Hiroaki Niimi , Brian Keith Kirkpatrick
发明人： James Joseph Chambers , Hiroaki Niimi , Brian Keith Kirkpatrick
IPC分类号： H01L21/02
CPC分类号： H01L29/78 , H01L21/28202 , H01L29/513 , H01L29/518
摘要： An integrated circuit (IC) includes a substrate having a top semiconductor surface including at least one MOS device including a source and a drain region spaced apart to define a channel region. A SiON gate dielectric layer that has a plurality of different N concentration portions is formed on the top semiconductor surface. A gate electrode is on the SiON layer. The plurality of different N concentration portions include (i) a bottom portion extending to the semiconductor interface having an average N concentration of 10 atomic %, and (iii) a top portion on the bulk portion extending to a gate electrode interface having an average N concentration that is ≧2 atomic % less than a peak N concentration of the bulk portion.
摘要翻译：集成电路（IC）包括具有顶部半导体表面的衬底，该顶部半导体表面包括至少一个MOS器件，其包括间隔开的源极和漏极区域以限定沟道区域。在顶部半导体表面上形成具有多个不同N个浓度部分的SiON栅介质层。栅电极位于SiON层上。多个不同的N个浓度部分包括（i）平均N浓度<2原子％延伸到半导体界面的底部，（ii）平均N浓度> 10原子％的本体部分，和（iii）本体部分的顶部延伸到具有比本体部分的峰值N浓度小> 2原子％的平均N浓度的栅电极界面。

35. 发明申请

US20110207314A1 Methods to Enhance Effective Work Function of Mid-Gap Metal by Incorporating Oxygen and Hydrogen at a Low Thermal Budget 审中-公开
标题翻译：通过在低热预算下引入氧气和氢气来提高中间金属有效功能的方法
公开(公告)号：US20110207314A1
公开(公告)日：2011-08-25
申请号：US13100474
申请日：2011-05-04
申请人： Hiroaki Niimi , James Joseph Chambers
发明人： Hiroaki Niimi , James Joseph Chambers
IPC分类号： H01L21/28
CPC分类号： H01L29/66545 , H01L21/02244 , H01L21/28088 , H01L21/28185 , H01L21/823842 , H01L21/823857 , H01L29/4966 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/7833
摘要： A process is disclosed of forming metal replacement gates for PMOS transistors with oxygen in the metal gates such that the PMOS gates have effective work functions above 4.85. Metal work function layers in the PMOS gates are oxidized at low temperature to increase their effective work functions to the desired PMOS range. Hydrogen may also be incorporated at an interface between the metal gates and underlying gate dielectrics. Materials for the metal work function layers and processes for the low temperature oxidation are disclosed.
摘要翻译：公开了一种用于在金属栅极中用氧形成PMOS晶体管的金属替代栅极的工艺，使得PMOS栅极具有高于4.85的有效功函数。 PMOS栅极中的金属功函数层在低温下被氧化，以将它们的有效功函数增加到期望的PMOS范围。氢也可以并入在金属栅极和下面的栅极电介质之间的界面处。公开了用于金属加工功能层的材料和用于低温氧化的方法。

36. 发明申请

US20110204454A1 SEMICONDUCTOR DEVICE INCLUDING SION GATE DIELECTRIC WITH PORTIONS HAVING DIFFERENT NITROGEN CONCENTRATIONS 有权
标题翻译：包括具有不同氮浓度的晶闸管电介质的半导体器件
公开(公告)号：US20110204454A1
公开(公告)日：2011-08-25
申请号：US12710709
申请日：2010-02-23
申请人： James Joseph Chambers , Hiroaki Niimi , Brian Keith Kirkpatrick
发明人： James Joseph Chambers , Hiroaki Niimi , Brian Keith Kirkpatrick
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78 , H01L21/28202 , H01L29/513 , H01L29/518
摘要： An integrated circuit (IC) includes a substrate having a top semiconductor surface including at least one MOS device including a source and a drain region spaced apart to define a channel region. A SiON gate dielectric layer that has a plurality of different N concentration portions is formed on the top semiconductor surface. A gate electrode is on the SiON layer. The plurality of different N concentration portions include (i) a bottom portion extending to the semiconductor interface having an average N concentration of 10 atomic %, and (iii) a top portion on the bulk portion extending to a gate electrode interface having an average N concentration that is ≧2 atomic % less than a peak N concentration of the bulk portion.
摘要翻译：集成电路（IC）包括具有顶部半导体表面的衬底，该顶部半导体表面包括至少一个MOS器件，其包括间隔开的源极和漏极区域以限定沟道区域。在顶部半导体表面上形成具有多个不同N个浓度部分的SiON栅介质层。栅电极位于SiON层上。多个不同的N个浓度部分包括（i）平均N浓度<2原子％延伸到半导体界面的底部，（ii）平均N浓度> 10原子％的本体部分，和（iii）本体部分的顶部延伸到具有比本体部分的峰值N浓度小2％原子％的平均N浓度的栅电极界面。

37. 发明授权

US07678675B2 Structure and method for a triple-gate transistor with reverse STI 有权
标题翻译：具有反向STI的三栅极晶体管的结构和方法
公开(公告)号：US07678675B2
公开(公告)日：2010-03-16
申请号：US11739567
申请日：2007-04-24
申请人： James Joseph Chambers , Mark Robert Visokay
发明人： James Joseph Chambers , Mark Robert Visokay
IPC分类号： H01L21/3205
CPC分类号： H01L29/7851 , H01L29/66795
摘要： Exemplary embodiments provide triple-gate semiconductor devices isolated by reverse STI structures and methodologies for their manufacture. In an exemplary process, stacked layers including a form layer over a dielectric layer can be formed over a semiconductor substrate. One or more trenches can be formed by etching through the stacked layers. The one or more trenches can be filled by an active area material to form one or more active areas, which can be isolated by remaining portions of the dielectric layer. Bodies of the active area material can be exposed by removing the form layer. One or more triple-gate devices can then be formed on the exposed active area material. The exemplary triple-gate semiconductor devices can control the dimensions for the active areas and provide less isolation spacing between the active areas, which optimizes manufacturing efficiency and device integration quality.
摘要翻译：示例性实施例提供了通过反向STI结构隔离的三栅半导体器件及其制造方法。在示例性工艺中，可以在半导体衬底上形成包括电介质层上的成形层的层叠层。可以通过蚀刻穿过层叠层而形成一个或多个沟槽。一个或多个沟槽可以由有源区域材料填充以形成一个或多个有源区域，其可以通过介电层的剩余部分来隔离。通过去除表层可以暴露活性区域材料的物质。然后可以在暴露的有源区域材料上形成一个或多个三栅极器件。示例性三栅极半导体器件可以控制有源区域的尺寸并且在有源区域之间提供更小的隔离间隔，这优化了制造效率和器件集成质量。

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