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31. 发明授权

US07989022B2 Methods of processing substrates, electrostatic carriers for retaining substrates for processing, and assemblies comprising electrostatic carriers having substrates electrostatically bonded thereto 有权
标题翻译：处理基板的方法，用于保持用于处理的基板的静电载体，以及包括静电载体的组件，所述静电载体具有静电键合的基板
公开(公告)号：US07989022B2
公开(公告)日：2011-08-02
申请号：US11780628
申请日：2007-07-20
申请人： Dewali Ray , Warren M. Farnworth , Kyle K. Kirby
发明人： Dewali Ray , Warren M. Farnworth , Kyle K. Kirby
IPC分类号： C23C16/00
CPC分类号： H01L21/6833
摘要： A method of processing a substrate includes physically contacting an exposed conductive electrode of an electrostatic carrier with a conductor to electrostatically bond a substrate to the electrostatic carrier. The conductor is removed from physically contacting the exposed conductive electrode. Dielectric material is applied over the conductive electrode. The substrate is treated while it is electrostatically bonded to the electrostatic carrier. In one embodiment, a conductor is forced through dielectric material that is received over a conductive electrode of an electrostatic carrier to physically contact the conductor with the conductive electrode to electrostatically bond a substrate to the electrostatic carrier. After removing the conductor from the dielectric material, the substrate is treated while it is electrostatically bonded to the electrostatic carrier. Electrostatic carriers for retaining substrates for processing, and such assemblies, are also disclosed.
摘要翻译：处理衬底的方法包括使静电载体的暴露的导电电极与导体物理接触，以将衬底静电结合到静电载体上。导体从物理接触暴露的导电电极去除。电介质材料施加在导电电极上。在静电接触静电载体的同时对衬底进行处理。在一个实施例中，将导体强制通过介电材料，其被接收在静电载体的导电电极上，以与导电电极物理接触导体，以使基板静电地接合到静电载体上。在从电介质材料中去除导体之后，将衬底静电结合到静电载体上进行处理。还公开了用于保持用于加工的基材和这种组件的静电载体。

32. 发明授权

US07915736B2 Microfeature workpieces and methods for forming interconnects in microfeature workpieces 有权
标题翻译：微型工件和在微型工件中形成互连的方法
公开(公告)号：US07915736B2
公开(公告)日：2011-03-29
申请号：US11832742
申请日：2007-08-02
申请人： Kyle K. Kirby , William M. Hiatt , Richard L. Stocks
发明人： Kyle K. Kirby , William M. Hiatt , Richard L. Stocks
IPC分类号： H01L23/48 , H01L23/52 , H01L23/40
CPC分类号： H01L21/76898 , H01L21/76868 , H01L21/76873 , H01L23/481 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. In one embodiment, a method of forming an interconnect in a microfeature workpiece includes forming a hole extending through a terminal and a dielectric layer to at least an intermediate depth in a substrate of a workpiece. The hole has a first lateral dimension in the dielectric layer and a second lateral dimension in the substrate proximate to an interface between the dielectric layer and the substrate. The second lateral dimension is greater than the first lateral dimension. The method further includes constructing an electrically conductive interconnect in at least a portion of the hole and in electrical contact with the terminal.
摘要翻译：在微型工件中形成互连的方法以及具有这种互连的微型工件在此公开。在一个实施例中，在微特征工件中形成互连的方法包括：将通过端子和电介质层延伸的孔形成在工件的衬底中的至少中间深度。该孔在电介质层中具有第一横向尺寸，并且该基板中的第二横向尺寸靠近介电层和基底之间的界面。第二横向尺寸大于第一横向尺寸。该方法还包括在孔的至少一部分中与端子电接触地构造导电互连。

33. 发明授权

US07829976B2 Microelectronic devices and methods for forming interconnects in microelectronic devices 有权
标题翻译：用于在微电子器件中形成互连的微电子器件和方法
公开(公告)号：US07829976B2
公开(公告)日：2010-11-09
申请号：US12419029
申请日：2009-04-06
申请人： Kyle K. Kirby , Salman Akram , David R. Hembree , Sidney B. Rigg , Warren M. Farnworth , William M. Hiatt
发明人： Kyle K. Kirby , Salman Akram , David R. Hembree , Sidney B. Rigg , Warren M. Farnworth , William M. Hiatt
IPC分类号： H01L29/40
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/48 , H01L2224/48091 , H01L2224/48465 , H01L2924/00014 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H05K1/0306 , H05K3/4038 , H05K3/422 , H05K3/423 , H05K2201/0305 , H05K2201/09827 , H05K2203/072 , H05K2203/1147 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelectronic die including an integrated circuit and a terminal operatively coupled to the integrated circuit. The method also includes forming a passage at least partially through the substrate and having an opening at the front side and/or backside of the substrate. The method further includes sealing the opening with a conductive cap that closes one end of the passage while another end of the passage remains open. The method then includes filling the passage with a conductive material.
摘要翻译：本文公开了微电子器件，用于封装微电子器件的方法，以及用于在微电子器件中形成互连的方法。在一个实施例中，一种方法包括提供具有正面和背面的微电子衬底。衬底具有包括集成电路的微电子管芯和可操作地耦合到集成电路的端子。该方法还包括至少部分地形成通过基底并且在基底的前侧和/或后侧具有开口的通道。该方法还包括用封闭通道一端的导电盖密封开口，同时通道的另一端保持打开。该方法然后包括用导电材料填充通道。

34. 发明授权

US07547850B2 Semiconductor device assemblies with compliant spring contact structures 有权
标题翻译：具有柔性弹簧接触结构的半导体器件组件
公开(公告)号：US07547850B2
公开(公告)日：2009-06-16
申请号：US11476471
申请日：2006-06-28
申请人： Kyle K. Kirby , Warren M. Farnworth
发明人： Kyle K. Kirby , Warren M. Farnworth
IPC分类号： H05K1/16
CPC分类号： H01L23/49811 , B33Y80/00 , G01R1/06727 , G01R1/07357 , G01R3/00 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/48 , H01L24/72 , H01L24/81 , H01L2224/13099 , H01L2224/13111 , H01L2224/136 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/8121 , H01L2224/81815 , H01L2224/81903 , H01L2224/83102 , H01L2224/92125 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/01051 , H01L2924/01072 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15787 , H01L2924/16152 , H01L2924/351 , H05K3/4092 , H05K2201/0311 , Y10T29/49204 , Y10T29/49222 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Photolithography patterned spring contacts are disclosed. The spring contacts may be fabricated using thin film processing techniques. A substrate, such as a silicon wafer or a carrier substrate is provided. At least one layer of a metal or alloy film may be deposited on the substrate or on at least one intervening release layer and patterned to form metal traces. A stressable material, exhibiting an at least partially tensile stress state, may be deposited on the metal traces in a localized region. A portion of the substrate or a portion of the intervening release layer underneath the metal traces may be removed by etching, causing the metal traces to curl upward resulting in the spring contacts. The spring contacts may be used as compliant electrical contacts for electrical devices, such as integrated circuits or carrier substrates. The compliant electrical contacts may also be used for probe cards to test other electrical devices.
摘要翻译：公开了光刻图案的弹簧触点。可以使用薄膜处理技术来制造弹簧触点。提供了诸如硅晶片或载体衬底的衬底。至少一层金属或合金膜可以沉积在衬底上或至少一个中间释放层上并且被图案化以形成金属迹线。表现出至少部分拉伸应力状态的可压应材料可以沉积在局部区域的金属迹线上。可以通过蚀刻去除基底的一部分或金属迹线下方的中间释放层的一部分，导致金属迹线向上卷曲，导致弹簧接触。弹簧触点可以用作电气装置的柔性电触点，例如集成电路或载体基板。兼容的电触点也可用于探针卡以测试其他电气设备。

35. 发明授权

US07498647B2 Packaged microelectronic imagers and methods of packaging microelectronic imagers 有权
标题翻译：封装的微电子成像器和包装微电子成像器的方法
公开(公告)号：US07498647B2
公开(公告)日：2009-03-03
申请号：US10864974
申请日：2004-06-10
申请人： Kyle K. Kirby , Salman Akram , William M. Hiatt
发明人： Kyle K. Kirby , Salman Akram , William M. Hiatt
IPC分类号： H01L21/00
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/48 , H01L27/14618 , H01L27/14625 , H01L31/0203 , H01L31/02325 , H01L2224/48227 , H01L2924/00014 , H01L2924/01029 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/04941 , H01L2924/12042 , H01L2924/14 , H01L2924/15174 , H04N5/2257 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrate, an integrated circuit, and an image sensor electrically coupled to the integrated circuit. A bond-pad is carried by the substrate and electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends partially through the substrate and is in contact with the bond-pad. The interconnect can include a passage extending partially through the substrate to the bond-pad, a dielectric liner deposited into the passage and in contact with the substrate, a conductive layer deposited onto at least a portion of the dielectric liner, a wetting agent deposited onto at least a portion of the conductive layer, and a conductive fill material deposited into the passage and electrically coupled to the bond-pad.
摘要翻译：本文公开了微电子成像器，用于封装微电子成像器的方法，以及用于在微电子成像器中形成导电晶片间互连的方法。在一个实施例中，微电子成像管芯可以包括微电子衬底，集成电路和电耦合到集成电路的图像传感器。接合焊盘由衬底承载并电耦合到集成电路。导电晶片互连部分地穿过衬底延伸并与焊盘接触。互连可以包括部分地延伸穿过衬底到接合焊盘的通道，沉积到通道中并与衬底接触的介电衬垫，沉积在电介质衬垫的至少一部分上的导电层，沉积在电介质衬垫上的润湿剂所述导电层的至少一部分以及沉积到所述通道中并电耦合到所述接合焊盘的导电填充材料。

36. 发明授权

US07452743B2 Microelectronic imaging units and methods of manufacturing microelectronic imaging units at the wafer level 有权
标题翻译：微电子成像单元和在晶片级制造微电子成像单元的方法
公开(公告)号：US07452743B2
公开(公告)日：2008-11-18
申请号：US11217877
申请日：2005-09-01
申请人： Steven D. Oliver , Lu Velicky , William Mark Hiatt , David R. Hembree , Mark E. Tuttle , Sidney B. Rigg , James M. Wark , Warren M. Farnworth , Kyle K. Kirby
发明人： Steven D. Oliver , Lu Velicky , William Mark Hiatt , David R. Hembree , Mark E. Tuttle , Sidney B. Rigg , James M. Wark , Warren M. Farnworth , Kyle K. Kirby
IPC分类号： H01L21/00
CPC分类号： H01L21/00 , H01L21/76898 , H01L23/552 , H01L27/14609 , H01L27/14618 , H01L27/14621 , H01L27/14623 , H01L27/14627 , H01L27/14632 , H01L27/14636 , H01L27/14685 , H01L27/14687 , H01L2924/0002 , H01L2924/00
摘要： Microelectronic imaging units and methods for manufacturing a plurality of imaging units at the wafer level are disclosed herein. In one embodiment, a method for manufacturing a plurality of imaging units includes providing an imager workpiece having a plurality of imaging dies including integrated circuits, external contacts electrically coupled to the integrated circuits, and image sensors operably coupled to the integrated circuits. The individual image sensors include at least one dark current pixel at a perimeter portion of the image sensor. The method includes depositing a cover layer onto the workpiece and over the image sensors. The method further includes patterning and selectively developing the cover layer to form discrete volumes of cover layer material over corresponding image sensors. The discrete volumes of cover layer material have sidewalls aligned with an inboard edge of the individual dark current pixels such that the dark current pixels are not covered by the discrete volumes.
摘要翻译：本文公开了用于在晶片级制造多个成像单元的微电子成像单元和方法。在一个实施例中，制造多个成像单元的方法包括提供具有多个成像管芯的成像工件，所述成像管芯包括集成电路，电耦合到集成电路的外部触点以及可操作地耦合到集成电路的图像传感器。各个图像传感器包括在图像传感器的周边部分处的至少一个暗电流像素。该方法包括将覆盖层沉积在工件上并在图像传感器上方。该方法还包括图案化和选择性地显影覆盖层以在对应的图像传感器上形成分离体积的覆盖层材料。覆盖层材料的离散体积具有与各个暗电流像素的内侧边缘对准的侧壁，使得暗电流像素不被离散体积覆盖。

37. 发明授权

US07449910B2 Test system for semiconductor components having conductive spring contacts 失效
标题翻译：具有导电弹簧触点的半导体部件的测试系统
公开(公告)号：US07449910B2
公开(公告)日：2008-11-11
申请号：US11348094
申请日：2006-02-06
申请人： Kyle K. Kirby , Warren M. Farnworth
发明人： Kyle K. Kirby , Warren M. Farnworth
IPC分类号： G01R31/26
CPC分类号： G01R1/06733 , B33Y70/00 , B33Y80/00 , G01R1/06711 , G01R1/07314 , G01R3/00 , H01L23/49811 , H01L24/72 , H01L2224/05571 , H01L2224/05573 , H01L2224/13011 , H01L2224/13019 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01009 , H01L2924/01012 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01082 , H01L2924/12042 , H01L2924/14 , H05K3/326 , H05K3/4092 , H01L2924/00 , H01L2224/05599
摘要： An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer formed as a conductive spring element. In addition, the complaint conductive layer includes a tip for engaging the component contact and a spring segment portion for resiliently supporting the tip. A method for fabricating the interconnect includes the steps of shaping the substrate, forming a conductive layer on a shaped portion of the substrate and removing at least some of the shaped portion. The shaped portion can comprise a raised step or dome, or a shaped recess in the substrate. The conductive layer can comprise a metal, a conductive polymer or a polymer tape can include a penetrating structure or penetrating particles. The interconnect can be used to construct wafer level test systems, and die level test systems as well, for semiconductor components such as wafers, dice and packages.
摘要翻译：用于测试半导体部件的互连件包括衬底，以及被配置为电接合半导体部件上的部件触点的衬底上的互连触点。每个互连触点包括形成为导电弹簧元件的柔性导电层。此外，投诉导电层包括用于接合部件触点的尖端和用于弹性地支撑尖端的弹簧部分部分。一种用于制造互连的方法包括以下步骤：对衬底进行成形，在衬底的成形部分上形成导电层，并移除至少部分成形部分。成形部分可以包括升高的台阶或圆顶，或者基板中的成形凹部。导电层可以包括金属，导电聚合物或聚合物带可以包括穿透结构或穿透颗粒。互连可以用于构建晶片级测试系统和芯片级测试系统，用于诸如晶片，芯片和封装的半导体元件。

38. 发明授权

US07411304B2 Semiconductor interconnect having conductive spring contacts 失效
标题翻译：具有导电弹簧触点的半导体互连
公开(公告)号：US07411304B2
公开(公告)日：2008-08-12
申请号：US11031160
申请日：2005-01-06
申请人： Kyle K. Kirby , Warren M. Farnworth
发明人： Kyle K. Kirby , Warren M. Farnworth
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： G01R1/06733 , B33Y70/00 , B33Y80/00 , G01R1/06711 , G01R1/07314 , G01R3/00 , H01L23/49811 , H01L24/72 , H01L2224/05571 , H01L2224/05573 , H01L2224/13011 , H01L2224/13019 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01009 , H01L2924/01012 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01082 , H01L2924/12042 , H01L2924/14 , H05K3/326 , H05K3/4092 , H01L2924/00 , H01L2224/05599
摘要： An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer formed as a conductive spring element. In addition, the complaint conductive layer includes a tip for engaging the component contact and a spring segment portion for resiliently supporting the tip. A method for fabricating the interconnect includes the steps of shaping the substrate, forming a conductive layer on a shaped portion of the substrate and removing at least some of the shaped portion. The shaped portion can comprise a raised step or dome, or a shaped recess in the substrate. The conductive layer can comprise a metal, a conductive polymer or a polymer tape can include a penetrating structure or penetrating particles. The interconnect can be used to construct wafer level test systems, and die level test systems as well, for semiconductor components such as wafers, dice and packages.
摘要翻译：用于测试半导体部件的互连件包括衬底，以及被配置为电接合半导体部件上的部件触点的衬底上的互连触点。每个互连触点包括形成为导电弹簧元件的柔性导电层。此外，投诉导电层包括用于接合部件触点的尖端和用于弹性地支撑尖端的弹簧部分部分。一种用于制造互连的方法包括以下步骤：对衬底进行成形，在衬底的成形部分上形成导电层，并移除至少部分成形部分。成形部分可以包括升高的台阶或圆顶，或者基板中的成形凹部。导电层可以包括金属，导电聚合物或聚合物带可以包括穿透结构或穿透颗粒。互连可以用于构建晶片级测试系统和芯片级测试系统，用于诸如晶片，芯片和封装的半导体元件。

39. 发明授权

US07332413B2 Semiconductor wafers including one or more reinforcement structures and methods of forming the same 有权
标题翻译：包括一个或多个增强结构的半导体晶片及其形成方法
公开(公告)号：US07332413B2
公开(公告)日：2008-02-19
申请号：US11516095
申请日：2006-09-05
申请人： Kyle K. Kirby
发明人： Kyle K. Kirby
IPC分类号： H01L21/30
CPC分类号： H01L29/0657 , H01L21/02002 , H01L21/02035 , H01L21/304 , H01L21/78 , Y10S438/977
摘要： Methods of forming semiconductor devices include thinning a region of a semiconductor wafer and forming at least one semiconductor die laterally within a thinned region of the wafer. One or more reinforcement structures may be defined on the wafer. Semiconductor wafers include one or more reinforcement structures that extend laterally along the wafer and project from at least one surface of the wafer. The wafers further include a plurality of at least partially formed semiconductor dice laterally within at least one region having a thickness that is less than a thickness of the reinforcement structures. The wafers may include a plurality of at least partially formed semiconductor dice laterally within each of a plurality of thin regions defined between a plurality of reinforcement structures. The thin regions may have an average thickness less than an average thickness of the reinforcement structures.
摘要翻译：形成半导体器件的方法包括使半导体晶片的区域变薄并且在晶片的薄化区域内横向形成至少一个半导体晶片。可以在晶片上限定一个或多个加强结构。半导体晶片包括沿着晶片横向延伸并从晶片的至少一个表面突出的一个或多个加强结构。晶片进一步包括多个至少部分形成的半导体晶片，其至少一个区域内具有小于加强结构厚度的厚度。晶片可以在多个加强结构之间限定的多个薄区域的每一个内横向包括多个至少部分形成的半导体晶片。薄区域可以具有小于加强结构的平均厚度的平均厚度。

40. 发明授权

US07288954B2 Compliant contact pin test assembly and methods thereof 有权
标题翻译：符合接触针测试组件及其方法
公开(公告)号：US07288954B2
公开(公告)日：2007-10-30
申请号：US11477217
申请日：2006-06-29
申请人： Kyle K. Kirby , Warren M. Farnworth , James M. Wark , William M. Hiatt , David R. Hembree , Alan G. Wood
发明人： Kyle K. Kirby , Warren M. Farnworth , James M. Wark , William M. Hiatt , David R. Hembree , Alan G. Wood
IPC分类号： G01R31/02
CPC分类号： G01R1/0735 , G01R1/07314 , H01L23/13 , H01L23/481 , H01L23/49811 , H01L23/49827 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16235 , H01L2924/00014 , H01L2924/09701 , H01L2924/15311 , H01L2924/3511 , H01R12/714 , H01R13/24 , H01R2201/20 , H05K3/326 , H05K7/1069 , H05K2201/0314 , H05K2201/09036 , H05K2201/10378 , Y10T29/49165 , Y10T29/49174 , Y10T29/49204 , Y10T29/49222 , H01L2224/05599
摘要： A compliant contact pin assembly and a contactor card and methods for testing therewith are provided. The compliant contact pin assembly includes a contact pin formed from a portion of a substrate with the contact pin compliantly held suspended within the substrate by a compliant coupling structure. The suspension within the substrate results in a compliant deflection orthogonal to the plane of the substrate. The contact pin assembly is formed by generally thinning the substrate around the contact pin location and then specifically thinning the substrate immediately around the contact pin location for forming a void. The contact pin is compliantly coupled, in one embodiment by compliant coupling material, and in another embodiment by compliantly flexible portions of the substrate.
摘要翻译：提供了一种柔性接触销组件和接触器卡以及用于测试的方法。柔性接触销组件包括由基板的一部分形成的接触销，其中触头销顺从地保持通过柔性联接结构悬挂在基板内。衬底内的悬浮液导致与衬底的平面垂直的柔顺偏转。接触销组件通过使基板围绕接触销位置大体变薄而形成，然后特别地使基板在接触销位置周围特别地变薄以形成空隙。在一个实施例中，接触销被顺从地联接，在一个实施例中通过柔性耦合材料，并且在另一个实施例中，通过柔性柔性部分的衬底。

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