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31. 发明申请

US20100181671A1 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100181671A1
公开(公告)日：2010-07-22
申请号：US12688557
申请日：2010-01-15
申请人： Jin-Ho Park , Gil-Heyun Choi , Byung-Lyul Park , Jong-Myeong Lee , Zung-Sun Choi , Hye-Kyung Jung
发明人： Jin-Ho Park , Gil-Heyun Choi , Byung-Lyul Park , Jong-Myeong Lee , Zung-Sun Choi , Hye-Kyung Jung
IPC分类号： H01L23/532 , H01L23/522 , H01L21/768
CPC分类号： H01L21/76846 , H01L21/28562 , H01L21/76856 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L27/10855 , H01L27/11521 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device can include an insulation layer on that is on a substrate on which a plurality of lower conductive structures are formed, where the insulation layer has an opening. A barrier layer is on a sidewall and a bottom of the opening of the insulation layer, where the barrier layer includes a first barrier layer in which a constituent of a first deoxidizing material is richer than a metal material in the first barrier layer and a second barrier layer in which a metal material in the second barrier layer is richer than a constituent of a second deoxidizing material. An interconnection is in the opening of which the sidewall and the bottom are covered with the barrier layer, the interconnection is electrically connected to the lower conductive structure.
摘要翻译：半导体器件可以包括在其上形成有多个下导电结构的基板上的绝缘层，其中绝缘层具有开口。阻挡层位于绝缘层的开口的侧壁和底部上，其中阻挡层包括第一阻挡层，第一脱氧材料的成分比第一阻挡层中的金属材料更富，第二阻隔层阻挡层，其中第二阻挡层中的金属材料比第二脱氧材料的成分更富。互连在其开口中，侧壁和底部被阻挡层覆盖，互连电连接到下导电结构。

32. 发明授权

US09171753B2 Semiconductor devices having conductive via structures and methods for fabricating the same 有权
标题翻译：具有导电通孔结构的半导体器件及其制造方法
公开(公告)号：US09171753B2
公开(公告)日：2015-10-27
申请号：US13758239
申请日：2013-02-04
申请人： Ho-Jin Lee , Kyu-ha Lee , Gilheyun Choi , YongSoon Choi , Pil-Kyu Kang , Byung-Lyul Park , Hyunsoo Chung
发明人： Ho-Jin Lee , Kyu-ha Lee , Gilheyun Choi , YongSoon Choi , Pil-Kyu Kang , Byung-Lyul Park , Hyunsoo Chung
IPC分类号： H01L21/768 , H01L23/00 , H01L23/48 , H01L21/02 , H01L25/065 , H01L23/31 , H01L21/683
CPC分类号： H01L21/768 , H01L21/02271 , H01L21/6836 , H01L21/76898 , H01L23/3192 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/13 , H01L25/0657 , H01L2221/68372 , H01L2224/02372 , H01L2224/0401 , H01L2224/05009 , H01L2224/05027 , H01L2224/05548 , H01L2224/05567 , H01L2224/05568 , H01L2224/0557 , H01L2224/05571 , H01L2224/06181 , H01L2224/13006 , H01L2224/13009 , H01L2224/13022 , H01L2224/13023 , H01L2224/13025 , H01L2224/13076 , H01L2224/13082 , H01L2224/131 , H01L2224/14181 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06565 , H01L2924/00014 , H01L2924/181 , H01L2924/351 , H01L2924/00012 , H01L2924/014 , H01L2224/05552 , H01L2924/00
摘要： In one embodiment, the method includes forming a conductive via structure in a base layer. The base layer has a first surface and a second surface, and the second surface is opposite the first surface. The method further includes removing the second surface of the base layer to expose the conductive via structure such that the conductive via structure protrudes from the second surface, and forming a first lower insulating layer over the second surface such that an end surface of the conductive via structure remains exposed by the first lower insulating layer.
摘要翻译：在一个实施例中，该方法包括在基层中形成导电通孔结构。基层具有第一表面和第二表面，并且第二表面与第一表面相对。该方法还包括去除基底层的第二表面以暴露导电通路结构，使得导电通孔结构从第二表面突出，并且在第二表面上形成第一下绝缘层，使得导电通孔的端表面结构保持由第一下绝缘层暴露。

33. 发明申请

US20160086874A1 SEMICONDUCTOR DEVICES INCLUDING THROUGH-SILICON-VIAS AND METHODS OF MANUFACTURING THE SAME AND SEMICONDUCTOR PACKAGES INCLUDING THE SEMICONDUCTOR DEVICES 审中-公开
标题翻译：包括硅 - 半导体的半导体器件及其制造方法和包括半导体器件的半导体器件
公开(公告)号：US20160086874A1
公开(公告)日：2016-03-24
申请号：US14858572
申请日：2015-09-18
申请人： Ju-Il Choi , Kwang-Jin Moon , Byung-Lyul Park , Jin-Ho An , Atsushi Fujisaki
发明人： Ju-Il Choi , Kwang-Jin Moon , Byung-Lyul Park , Jin-Ho An , Atsushi Fujisaki
IPC分类号： H01L23/48 , H01L23/532 , H01L23/528 , H01L23/00
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/5329 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L25/0657 , H01L25/18 , H01L2224/03618 , H01L2224/0401 , H01L2224/05018 , H01L2224/05025 , H01L2224/05027 , H01L2224/05155 , H01L2224/05546 , H01L2224/05557 , H01L2224/05559 , H01L2224/05564 , H01L2224/05567 , H01L2224/05572 , H01L2224/05611 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/05684 , H01L2224/06181 , H01L2224/13023 , H01L2224/13139 , H01L2224/13147 , H01L2224/16013 , H01L2224/16113 , H01L2224/16145 , H01L2224/16146 , H01L2224/16147 , H01L2224/16148 , H01L2224/16227 , H01L2224/32145 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/15311 , H01L2924/00 , H01L2924/00014 , H01L2924/013 , H01L2924/01047
摘要： A semiconductor device can include a substrate that has a surface. A via structure can extend through the substrate toward the surface of the substrate, where the via structure includes an upper surface. A pad structure can be on the surface of the substrate, where the pad structure can include a lower surface having at least one protrusion that is configured to protrude toward the upper surface of the via structure.
摘要翻译：半导体器件可以包括具有表面的衬底。通孔结构可以延伸穿过衬底朝向衬底的表面，其中通孔结构包括上表面。衬垫结构可以在衬底的表面上，其中衬垫结构可以包括具有至少一个突起的下表面，其被配置为朝向通孔结构的上表面突出。

34. 发明授权

US09379042B2 Integrated circuit devices having through silicon via structures and methods of manufacturing the same 有权
标题翻译：具有硅通孔结构的集成电路器件及其制造方法
公开(公告)号：US09379042B2
公开(公告)日：2016-06-28
申请号：US14504647
申请日：2014-10-02
申请人： Jae-Hwa Park , Suk-Chul Bang , Byung-Lyul Park , Kwang-Jin Moon
发明人： Jae-Hwa Park , Suk-Chul Bang , Byung-Lyul Park , Kwang-Jin Moon
IPC分类号： H01L21/02 , H01L23/48 , H01L49/02 , H01L21/768 , H01L27/108 , H01L23/522 , H01L23/538
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/522 , H01L23/5384 , H01L27/10814 , H01L27/10817 , H01L27/10823 , H01L27/10855 , H01L27/10888 , H01L27/10894 , H01L27/10897 , H01L28/87 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device is provided. The integrated circuit device includes: a capacitor including an electrode formed in a first area on a substrate; a through-silicon-via (TSV) landing pad formed in a second area on the substrate, the TSV landing pad including the same material as the electrode; a multi-layered interconnection structure formed on the capacitor and the TSV landing pad; and a TSV structure passing through the substrate, the TSV structure being connected to the multi-layered interconnection structure through the TSV landing pad.
摘要翻译：提供集成电路装置。集成电路装置包括：电容器，包括形成在基板上的第一区域中的电极; 形成在所述基板上的第二区域中的通硅通孔（TSV）着陆焊盘，所述TSV着陆焊盘包括与所述电极相同的材料; 形成在电容器和TSV着陆板上的多层互连结构; TSV结构通过基板，TSV结构通过TSV着陆焊盘连接到多层互连结构。

35. 发明申请

US20150108605A1 Integrated Circuit Devices Having Through Silicon Via Structures and Methods of Manufacturing the Same 有权
标题翻译：具有通过硅结构的集成电路器件及其制造方法
公开(公告)号：US20150108605A1
公开(公告)日：2015-04-23
申请号：US14504647
申请日：2014-10-02
申请人： Jae-Hwa Park , Suk-Chul Bang , Byung-Lyul Park , Kwang-Jin Moon
发明人： Jae-Hwa Park , Suk-Chul Bang , Byung-Lyul Park , Kwang-Jin Moon
IPC分类号： H01L23/50 , H01L49/02 , H01L27/108 , H01L23/48
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/522 , H01L23/5384 , H01L27/10814 , H01L27/10817 , H01L27/10823 , H01L27/10855 , H01L27/10888 , H01L27/10894 , H01L27/10897 , H01L28/87 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device is provided. The integrated circuit device includes: a capacitor including an electrode formed in a first area on a substrate; a through-silicon-via (TSV) landing pad formed in a second area on the substrate, the TSV landing pad including the same material as the electrode; a multi-layered interconnection structure formed on the capacitor and the TSV landing pad; and a TSV structure passing through the substrate, the TSV structure being connected to the multi-layered interconnection structure through the TSV landing pad.
摘要翻译：提供集成电路装置。集成电路装置包括：电容器，包括形成在基板上的第一区域中的电极; 形成在所述基板上的第二区域中的通硅通孔（TSV）着陆焊盘，所述TSV着陆焊盘包括与所述电极相同的材料; 形成在电容器和TSV着陆板上的多层互连结构; TSV结构通过基板，TSV结构通过TSV着陆焊盘连接到多层互连结构。

36. 发明申请

US20150102395A1 SEMICONDUCTOR DEVICE INCLUDING DECOUPLING CAPACITOR AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：包括解除电容器的半导体器件及其形成方法
公开(公告)号：US20150102395A1
公开(公告)日：2015-04-16
申请号：US14511801
申请日：2014-10-10
申请人： Jae-Hwa Park , Kwang-Jin Moon , Byung-Lyul Park
发明人： Jae-Hwa Park , Kwang-Jin Moon , Byung-Lyul Park
IPC分类号： H01L27/108 , H01L23/64 , H01L49/02 , H01L23/48 , H01L29/423 , H01L29/51
CPC分类号： H01L23/481 , H01L23/642 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/0657 , H01L27/10808 , H01L27/10823 , H01L27/10894 , H01L29/4236 , H01L29/66181 , H01L29/945 , H01L2224/0401 , H01L2224/05009 , H01L2224/05568 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05669 , H01L2224/05681 , H01L2224/05684 , H01L2224/06181 , H01L2224/131 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2224/16235 , H01L2224/17181 , H01L2224/81411 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81466 , H01L2224/81469 , H01L2224/81481 , H01L2224/81484 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2225/06572 , H01L2924/1436 , H01L2924/15311 , H01L2924/19015 , H01L2924/19041 , H01L2924/19104 , H01L2924/014
摘要： An integrated circuit device includes a semiconductor substrate having first and second semiconductor regions therein, a gate trench in the first semiconductor region and a gate electrode in the gate trench. The gate electrode has an upper surface below a surface of the semiconductor substrate. A semiconductor well region is provided in the second semiconductor region. A capacitor trench extends in the semiconductor well region and an upper capacitor electrode extends in the capacitor trench. An electrical interconnect (e.g., conductive plug) is provided, which is electrically connected to the upper capacitor electrode at an interface therebetween. This interface has an upper surface below the surface of the semiconductor substrate.
摘要翻译：集成电路器件包括其中具有第一和第二半导体区域的半导体衬底，第一半导体区域中的栅极沟槽和栅极沟槽中的栅电极。栅电极在半导体衬底的表面下方具有上表面。半导体阱区域设置在第二半导体区域中。电容器沟槽在半导体阱区域中延伸，并且上电容器电极在电容器沟槽中延伸。提供电互连（例如，导电插头），其在它们之间的界面处电连接到上电容器电极。该界面在半导体衬底的表面下方具有上表面。

37. 发明授权

US07737038B2 Method of fabricating semiconductor device including planarizing conductive layer using parameters of pattern density and depth of trenches 有权
标题翻译：使用图案密度和沟槽深度的参数制造半导体器件的方法包括平坦化导电层
公开(公告)号：US07737038B2
公开(公告)日：2010-06-15
申请号：US11567927
申请日：2006-12-07
申请人： Seung-Mahn Lee , Byung-Lyul Park , MooJin Jung
发明人： Seung-Mahn Lee , Byung-Lyul Park , MooJin Jung
IPC分类号： H01L21/302
CPC分类号： H01L21/3212 , B24B37/013 , B24B49/105 , H01L22/26 , H01L2924/0002 , Y10S438/959 , H01L2924/00
摘要： A method of fabricating a semiconductor device includes forming a conductive layer on an insulating layer having a plurality of trenches on a semiconductor substrate, such that the conductive layer fills in the plurality of trenches formed in the insulating layer, and calculating a target eddy current value to measure an end point using parameters of a pattern density and a depth of the trenches. The method further includes planarizing the conductive layer and measuring eddy current values on the conductive layer using an eddy current monitoring system, and stopping the planarization when the measured eddy current value reaches the target eddy current value to form a planarized conductive layer having a target height on the insulating layer.
摘要翻译：一种制造半导体器件的方法包括在半导体衬底上在具有多个沟槽的绝缘层上形成导电层，使得导电层填充在绝缘层中形成的多个沟槽中，并计算目标涡流值使用模式密度和沟槽深度的参数来测量终点。该方法还包括使用涡流监测系统平坦化导电层并测量导电层上的涡流值，并且当测量的涡流值达到目标涡流值时停止平坦化，以形成具有目标高度的平坦化导电层在绝缘层上。

38. 发明授权

US07348277B2 Methods of fabricating semiconductor device using sacrificial layer 有权
标题翻译：使用牺牲层制造半导体器件的方法
公开(公告)号：US07348277B2
公开(公告)日：2008-03-25
申请号：US11352640
申请日：2006-02-13
申请人： Ja-Eung Koo , Byung-Lyul Park
发明人： Ja-Eung Koo , Byung-Lyul Park
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/7688 , H01L21/76819
摘要： There are provided methods of fabricating a semiconductor device using a sacrificial layer. The methods provide an approach to maintaining thickness distribution of the interlayer insulating layers below a sacrificial layer uniform on an overall surface of a semiconductor substrate during performing a chemical mechanical polishing (CMP) process in a damascene process. To this end, the method includes forming a pad layer, a pad interlayer insulating layer, an etch stop layer pattern, a planarized interlayer insulating layer and a sacrificial layer sequentially on a semiconductor substrate. At least one trench is formed in the sacrificial layer and the planarized interlayer insulating layer. A via contact hole is formed in the etch stop layer pattern, the pad interlayer insulating layer, and the pad layer to be disposed below the trench. A diffusion barrier layer and a conductive layer are sequentially formed to fill the trench and the via contact hole. A CMP process is performed on the conductive layer, the diffusion barrier layer, and the sacrificial layer.
摘要翻译：提供了使用牺牲层制造半导体器件的方法。这些方法提供了一种在大理石工艺中进行化学机械抛光（CMP）工艺期间，在半导体衬底的整个表面上均匀地保持牺牲层的厚度分布的方法。为此，该方法包括在半导体衬底上依次形成焊盘层，焊盘层间绝缘层，蚀刻停止层图案，平坦化的层间绝缘层和牺牲层。在牺牲层和平坦化层间绝缘层中形成至少一个沟槽。在蚀刻停止层图案，焊盘层间绝缘层和焊盘层中形成通孔接触孔，以设置在沟槽下方。依次形成扩散阻挡层和导电层以填充沟槽和通孔接触孔。在导电层，扩散阻挡层和牺牲层上执行CMP工艺。

39. 发明申请

US20070196994A1 Method of Fabricating Semiconductor Device Including Planarizing Conductive Layer Using Parameters of Pattern Density and Depth of Trenches 有权
标题翻译：使用图案密度和沟槽深度的参数制造包括平面化导电层的半导体器件的方法
公开(公告)号：US20070196994A1
公开(公告)日：2007-08-23
申请号：US11567927
申请日：2006-12-07
申请人： Seung-Mahn Lee , Byung-Lyul Park , MooJin Jung
发明人： Seung-Mahn Lee , Byung-Lyul Park , MooJin Jung
IPC分类号： H01L21/20
CPC分类号： H01L21/3212 , B24B37/013 , B24B49/105 , H01L22/26 , H01L2924/0002 , Y10S438/959 , H01L2924/00
摘要： A method of fabricating a semiconductor device includes forming a conductive layer on an insulating layer having a plurality of trenches on a semiconductor substrate, such that the conductive layer fills in the plurality of trenches formed in the insulating layer, and calculating a target eddy current value to measure an end point using parameters of a pattern density and a depth of the trenches. The method further includes planarizing the conductive layer and measuring eddy current values on the conductive layer using an eddy current monitoring system, and stopping the planarization when the measured eddy current value reaches the target eddy current value to form a planarized conductive layer having a target height on the insulating layer.
摘要翻译：一种制造半导体器件的方法包括在半导体衬底上在具有多个沟槽的绝缘层上形成导电层，使得导电层填充在绝缘层中形成的多个沟槽中，并计算目标涡流值使用模式密度和沟槽深度的参数来测量终点。该方法还包括使用涡流监测系统平坦化导电层并测量导电层上的涡流值，并且当测量的涡流值达到目标涡流值时停止平坦化，以形成具有目标高度的平坦化导电层在绝缘层上。

40. 发明申请

US20060183333A1 Methods of fabricating semiconductor device using sacrificial layer 有权
标题翻译：使用牺牲层制造半导体器件的方法
公开(公告)号：US20060183333A1
公开(公告)日：2006-08-17
申请号：US11352640
申请日：2006-02-13
申请人： Ja-Eung Koo , Byung-Lyul Park
发明人： Ja-Eung Koo , Byung-Lyul Park
IPC分类号： H01L21/461 , C23F1/00 , B44C1/22
CPC分类号： H01L21/7688 , H01L21/76819
摘要： There are provided methods of fabricating a semiconductor device using a sacrificial layer. The methods provide an approach to maintaining thickness distribution of the interlayer insulating layers below a sacrificial layer uniform on an overall surface of a semiconductor substrate during performing a chemical mechanical polishing (CMP) process in a damascene process. To this end, the method includes forming a pad layer, a pad interlayer insulating layer, an etch stop layer pattern, a planarized interlayer insulating layer and a sacrificial layer sequentially on a semiconductor substrate. At least one trench is formed in the sacrificial layer and the planarized interlayer insulating layer. A via contact hole is formed in the etch stop layer pattern, the pad interlayer insulating layer, and the pad layer to be disposed below the trench. A diffusion barrier layer and a conductive layer are sequentially formed to fill the trench and the via contact hole. A CMP process is performed on the conductive layer, the diffusion barrier layer, and the sacrificial layer.
摘要翻译：提供了使用牺牲层制造半导体器件的方法。这些方法提供了一种在大理石过程中执行化学机械抛光（CMP）工艺期间，在半导体衬底的整个表面上均匀地保持牺牲层的厚度分布的方法。为此，该方法包括在半导体衬底上依次形成焊盘层，焊盘层间绝缘层，蚀刻停止层图案，平坦化的层间绝缘层和牺牲层。在牺牲层和平坦化层间绝缘层中形成至少一个沟槽。在蚀刻停止层图案，焊盘层间绝缘层和焊盘层中形成通孔接触孔，以设置在沟槽下方。依次形成扩散阻挡层和导电层以填充沟槽和通孔接触孔。在导电层，扩散阻挡层和牺牲层上执行CMP工艺。

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