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31. 发明授权

US06548423B1 Multilayer anti-reflective coating process for integrated circuit fabrication 有权
标题翻译：用于集成电路制造的多层抗反射涂层工艺
公开(公告)号：US06548423B1
公开(公告)日：2003-04-15
申请号：US10047971
申请日：2002-01-16
申请人： Marina V. Plat , Christopher F. Lyons , Scott A. Bell , Todd P. Lukanc
发明人： Marina V. Plat , Christopher F. Lyons , Scott A. Bell , Todd P. Lukanc
IPC分类号： H01L2131
CPC分类号： H01L21/0276 , G03F7/091 , H01L21/0332 , H01L21/28123 , H01L21/32139
摘要： A method utilizing a multilayer anti-reflective coating layer structure. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating.
摘要翻译：一种利用多层抗反射涂层结构的方法。多层抗反射涂层结构可以用作形成各种集成电路结构的硬掩模。可以使用多层抗反射涂层结构来形成由多晶硅和电介质层组成的栅叠层。在多层抗反射涂层上施加光致抗蚀剂。

32. 发明授权

US06458606B2 Etch bias distribution across semiconductor wafer 失效
标题翻译：半导体晶圆上的蚀刻偏压分布
公开(公告)号：US06458606B2
公开(公告)日：2002-10-01
申请号：US09854272
申请日：2001-05-11
申请人： Marina V. Plat , Luigi Capodieci , Scott A. Bell , Todd Lukanc
发明人： Marina V. Plat , Luigi Capodieci , Scott A. Bell , Todd Lukanc
IPC分类号： G01R3126
CPC分类号： H01L22/34
摘要： Test wafers used in the production of semiconductor wafers include a plurality of active structures which form operational circuitry of the test wafer. The active structures are densely populated in some areas of the test wafer and sparsely populated in other areas of the test wafer. It has been observed that critical dimensions such as etch bias and slope profiles of identical structures vary depending on whether the structure is formed in a densely or sparsely populated region. Dummy structures are formed on the test wafer so as to uniformly distribute the density of structures across the test wafer.
摘要翻译：用于生产半导体晶片的测试晶片包括形成测试晶片的操作电路的多个有源结构。活性结构密集地存在于测试晶片的某些区域，并且稀疏地填充在测试晶片的其它区域中。已经观察到，相同结构的临界尺寸，例如蚀刻偏压和斜率分布根据结构是否形成在密集或人烟稀少的区域中而变化。在测试晶片上形成虚拟结构，以便在测试晶片上均匀分布结构的密度。

33. 发明授权

US06423650B1 Ultra-thin resist coating quality by increasing surface roughness of the substrate 有权
公开(公告)号：US06423650B1
公开(公告)日：2002-07-23
申请号：US09371715
申请日：1999-08-09
申请人： Marina V. Plat , Christopher F. Lyons , Michael K. Templeton , Bhanwar Singh
发明人： Marina V. Plat , Christopher F. Lyons , Michael K. Templeton , Bhanwar Singh
IPC分类号： H01L2131
摘要： In one embodiment, the present invention relates to a method of processing a semiconductor substrate, involving the steps of providing the semiconductor substrate having an upper surface; roughening the upper surface of the semiconductor substrate so that the upper surface of the semiconductor substrate has an Rtm of about 10 Å or more; and depositing an ultra-thin photoresist on the upper surface of the semiconductor substrate, the ultra-thin photoresist having a thickness of about 2,000 Å or less.

34. 发明授权

US06210050B1 Resist developing method and apparatus with nozzle offset for uniform developer application 有权
标题翻译：用于均匀显影剂应用的具有喷嘴偏移的显影方法和装置
公开(公告)号：US06210050B1
公开(公告)日：2001-04-03
申请号：US09203297
申请日：1998-12-01
申请人： Marina V. Plat , Christopher F. Lyons
发明人： Marina V. Plat , Christopher F. Lyons
IPC分类号： G03D500
CPC分类号： G03F7/3021 , G03D5/04
摘要： A resist developing method and apparatus for developing resist formed on a semiconductor wafer includes a rotating platform for supporting the wafer and a nozzle for applying developer to the resist. The nozzle is situated above the wafer and is positioned to be offset from an axis of rotation of the wafer during application of the developer to the resist. During application of the developer, the wafer is rotated at a rotational speed which allows the developer to remain on the wafer without flowing past the semiconductor edges. The developer is preferably applied for a time period less than or equal to 2 seconds.
摘要翻译：用于在半导体晶片上形成的用于显影抗蚀剂的抗蚀剂显影方法和装置包括用于支撑晶片的旋转平台和用于将显影剂施加到抗蚀剂的喷嘴。喷嘴位于晶片上方并且被定位成在将显影剂施加到抗蚀剂期间偏离晶片的旋转轴线。在施加显影剂期间，晶片以允许显影剂保持在晶片上而不流过半导体边缘的转速旋转。显影剂优选地施加小于或等于2秒的时间。

35. 发明授权

US07964905B1 Anti-reflective interpoly dielectric 有权
标题翻译：防反射层间电介质
公开(公告)号：US07964905B1
公开(公告)日：2011-06-21
申请号：US09591266
申请日：2000-06-09
申请人： Robert B. Ogle, Jr. , Marina V. Plat , Mark T. Ramsbey
发明人： Robert B. Ogle, Jr. , Marina V. Plat , Mark T. Ramsbey
IPC分类号： H01L29/94
CPC分类号： H01L29/518 , H01L21/28273 , H01L29/42324 , H01L29/513
摘要： The invention provides core stacks for flash memory with an anti-reflective interpoly dielectric. Instead of requiring an anti-reflective coating at the top of the a stack, the present invention uses the interpoly layer as an anti-reflective coating in conjunction with a transmissive second polymer layer. Light is transmitted through the transmissive second polymer layer to the anti-reflective interpoly dielectric layer. The transmissive second polymer layer is formed from an amorphous silicon or polysilicon. Silicon oxynitride (SiON), as formed in the present invention, having a good dielectric constant K, is tailored in its index of refraction and in its thickness for utilization as both a good interpoly material and an anti-reflective coating.
摘要翻译：本发明提供了具有抗反射互聚电介质的闪存的核心堆叠。代替在堆叠的顶部需要抗反射涂层，本发明使用互聚层作为与透射性第二聚合物层结合的抗反射涂层。光通过透射的第二聚合物层传输到抗反射的多聚电介质层。透射的第二聚合物层由非晶硅或多晶硅形成。在本发明中形成的具有良好的介电常数K的氮氧化硅（SiON）在其折射率和其厚度方面被适应为良好的间隙材料和抗反射涂层。

36. 发明授权

US07368225B1 Two mask photoresist exposure pattern for dense and isolated regions 有权
标题翻译：两个掩模光刻胶曝光图案，用于密集和隔离的区域
公开(公告)号：US07368225B1
公开(公告)日：2008-05-06
申请号：US10925123
申请日：2004-08-24
申请人： Ramkumar Subramanian , Scott A. Bell , Todd P. Lukanc , Marina V. Plat , Uzodinma Okoroanyanwu , Hung-Eil Kim
发明人： Ramkumar Subramanian , Scott A. Bell , Todd P. Lukanc , Marina V. Plat , Uzodinma Okoroanyanwu , Hung-Eil Kim
IPC分类号： G03F7/00
CPC分类号： G03F1/00 , H01L21/76816
摘要： There is provided a method of making plurality of features in a first layer. A photoresist layer is formed over the first layer. Dense regions in the photoresist layer are exposed through a first mask under a first set of illumination conditions. Isolated regions in the photoresist layer are exposed through a second mask different from the first mask under a second set of illumination conditions different from the first set of illumination conditions. The exposed photoresist layer is patterned and then the first layer is patterned using the patterned photoresist layer as a mask.
摘要翻译：提供了在第一层中制作多个特征的方法。在第一层上形成光致抗蚀剂层。光致抗蚀剂层中的密集区域在第一组照射条件下通过第一掩模曝光。在与第一组照明条件不同的第二组照明条件下，光致抗蚀剂层中的隔离区域通过不同于第一掩模的第二掩模曝光。曝光的光致抗蚀剂层被图案化，然后使用图案化的光致抗蚀剂层作为掩模来对第一层进行图案化。

37. 发明授权

US07112489B1 Negative resist or dry develop process for forming middle of line implant layer 有权
标题翻译：用于形成线植入层中间的负阻抗或干式显影工艺
公开(公告)号：US07112489B1
公开(公告)日：2006-09-26
申请号：US11004691
申请日：2004-12-03
申请人： Christopher F. Lyons , Anna Minvielle , Marina V. Plat
发明人： Christopher F. Lyons , Anna Minvielle , Marina V. Plat
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L27/115 , H01L21/26513 , H01L27/11521
摘要： A method of implanting a middle of line (MOL) implant layer of a flash memory device that does not require a descumming step is disclosed. In a first embodiment, the method includes depositing a negative tone resist over the MOL implant layer. Portions of the negative tone resist in and above a plurality of trenches are not exposed to optical radiation, while portions surrounding the plurality of trenches are exposed. The unexposed portions are developed out thereby leaving a bottom surface of each trench substantially free of a resist residue. Implants can be placed in the MOL implant layer without the need for a descumming step. In a second embodiment, a bi-layer resist is deposited on the MOL implant layer, wherein the bi-layer resist includes a silicon containing top layer and a bottom layer. The bi-layer resist is patterned to expose a portion of the bottom layer that resides in and above a plurality of trenches. The bottom layer is dry etch developed using oxygen plasma as the etchant, thereby leaving a bottom surface of each trench substantially free of a resist residue. Implants can be placed in the MOL implant layer without the need for a descumming step.
摘要翻译：公开了一种注入不需要除尘步骤的闪速存储器件的中间线（MOL）注入层的方法。在第一实施例中，该方法包括在MOL植入层上沉积负色调抗蚀剂。在多个沟槽中和上方的负色调抗蚀剂的部分不暴露于光辐射，而围绕多个沟槽的部分被暴露。未曝光部分显影出来，从而留下每个沟槽的底表面基本上没有抗蚀剂残留物。植入物可以放置在MOL植入层中，而不需要除去步骤。在第二实施例中，双层抗蚀剂沉积在MOL注入层上，其中双层抗蚀剂包括含硅顶层和底层。图案化双层抗蚀剂以暴露驻留在多个沟槽中和上方的底层的一部分。底层是使用氧等离子体作为蚀刻剂进行干法蚀刻，从而留下每个沟槽的底表面基本上没有抗蚀剂残留物。植入物可以放置在MOL植入层中，而不需要除去步骤。

38. 发明授权

US07018922B1 Patterning for elongated VSS contact flash memory 有权
标题翻译：扩展VSS接触闪存的图案化
公开(公告)号：US07018922B1
公开(公告)日：2006-03-28
申请号：US10968713
申请日：2004-10-19
申请人： Hung-eil Kim , Anna Minvielle , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
发明人： Hung-eil Kim , Anna Minvielle , Christopher F. Lyons , Marina V. Plat , Ramkumar Subramanian
IPC分类号： H01L21/4763
CPC分类号： H01L27/11521 , H01L21/76802 , H01L27/115
摘要： A method of forming a contact in a flash memory device is disclosed. The method increases the depth of focus margin and the overlay margin between the contact and the stacked gate layers. A plurality of stacked gate layers are formed on a semiconductor substrate, wherein each stacked gate layer extends in a predefined direction and is substantially parallel to other stacked gate layers. An interlayer insulating layer is deposited over the plurality of stacked gate layers, and a contact hole is patterned between a first stacked gate layer of the plurality of stacked gate layers and a second stacked gate layer of the plurality of stacked gate layers. The contact hole is formed in an elongated shape, wherein a major axis of the contact hole is substantially parallel to the stacked gate layers. A conductive layer is deposited in the contact hole and excess conductive material is removed.
摘要翻译：公开了一种在闪速存储器件中形成触点的方法。该方法增加了接触和层叠栅极层之间的焦距裕度和覆盖边缘的深度。在半导体衬底上形成多个层叠的栅极层，其中每个堆叠的栅极层沿预定的方向延伸并且基本上平行于其它堆叠的栅极层。层叠绝缘层沉积在多个堆叠的栅极层上，并且在多个堆叠的栅极层的第一堆叠的栅极层和多个堆叠的栅极层的第二叠层栅极层之间形成接触孔。接触孔形成为细长形状，其中接触孔的长轴基本上平行于堆叠的栅极层。导电层沉积在接触孔中，去除过量的导电材料。

39. 发明授权

US06913958B1 Method for patterning a feature using a trimmed hardmask 失效
标题翻译：使用修剪后的硬掩模图案化特征的方法
公开(公告)号：US06913958B1
公开(公告)日：2005-07-05
申请号：US10366800
申请日：2003-02-14
申请人： Marina V. Plat , Marilyn I. Wright , Chih Yuh Yang , Douglas J. Bonser
发明人： Marina V. Plat , Marilyn I. Wright , Chih Yuh Yang , Douglas J. Bonser
IPC分类号： H01L21/033 , H01L21/28 , H01L21/311 , H01L21/3213 , H01L21/336 , H01L21/302 , H01L21/3205 , H01L21/84
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/28123 , H01L21/31116 , H01L21/31138 , H01L21/32139
摘要： In the formation of a semiconductor device, one or more hardmasks are formed during a process for patterning a device feature. One or more of the hardmasks is subjected to an isotropic etch to trim the hardmask prior to patterning an underlying layer. The trimmed hardmask layer is preferably an amorphous carbon layer.
摘要翻译：在形成半导体器件时，在用于图案化器件特征的工艺期间形成一个或多个硬掩模。对一个或多个硬掩模进行各向同性蚀刻，以在图案化底层之前对硬掩模进行修整。修整的硬掩模层优选为无定形碳层。

40. 发明授权

US06869888B1 E-beam flood exposure of spin-on material to eliminate voids in vias 失效
标题翻译：旋转材料的电子束暴露以消除通孔中的空隙
公开(公告)号：US06869888B1
公开(公告)日：2005-03-22
申请号：US09901704
申请日：2001-07-11
申请人： Marina V. Plat , Ramkumar Subramanian , Christopher F. Lyons , Bhanwar Singh
发明人： Marina V. Plat , Ramkumar Subramanian , Christopher F. Lyons , Bhanwar Singh
IPC分类号： H01L21/027 , H01L21/3105 , H01L21/312 , H01L21/768
CPC分类号： H01L21/76808 , H01L21/02118 , H01L21/0212 , H01L21/02134 , H01L21/0276 , H01L21/31058 , H01L21/312 , H01L21/76825
摘要： A method for forming a semiconductor device is described. The method comprises forming a first layer over a semiconductor substrate. At least one hole is formed through the first layer. A bottom anti-reflective coating (BARC) layer is formed in the at least one hole. The BARC layer is exposed to an electron beam (e-beam) so that the BARC layer reaches a flow temperature in the at least one hole. An etch is performed to form a trench in the first layer and over the at least one hole, wherein the BARC layer in the at least one hole acts as an etch resistant layer during the etch.
摘要翻译：对半导体装置的形成方法进行说明。该方法包括在半导体衬底上形成第一层。通过第一层形成至少一个孔。在至少一个孔中形成底部抗反射涂层（BARC）层。 BARC层暴露于电子束（电子束），使得BARC层在至少一个孔中达到流动温度。执行蚀刻以在第一层中和在至少一个孔上形成沟槽，其中至少一个孔中的BARC层在蚀刻期间用作耐蚀刻层。

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