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31. 发明授权

US5101503A Method of connecting channels of decentralized radio systems 失效
标题翻译：连接分散无线电系统的通道的方法
公开(公告)号：US5101503A
公开(公告)日：1992-03-31
申请号：US465320
申请日：1990-01-16
申请人： Yukitsuna Furuya
发明人： Yukitsuna Furuya
IPC分类号： H04M1/725 , H04W36/16 , H04W72/02 , H04W72/06
CPC分类号： H04W36/16 , H04M1/72511 , H04W72/02 , H04W72/06
摘要： In a method of connecting channels of a plurality of decentralized radio systems which perform independent channel connections, each of the plurality of radio systems sets a given channel and monitors a reception signal level of the given channel. Each radio system detects that the given channel is busy and sets a next channel when the reception signal level of the given channel is higher than a level corresponding to a threshold value. Each radio system rejects a connection if all channels are busy. Each radio system detects the given channel as an empty channel and starts communication through the given channel if the reception signal channel is lower than the level corresponding to the threshold value. Each radio system increases the threshold value when the channel connection is rejected. Each radio system decreases the threshold value when the communication is started.
摘要翻译：在连接执行独立信道连接的多个分散无线电系统的信道的方法中，多个无线系统中的每一个设置给定信道并监视给定信道的接收信号电平。当给定信道的接收信号电平高于对应于阈值的电平时，每个无线电系统检测给定信道是忙的并且设置下一个信道。如果所有频道都忙，则每个无线电系统拒绝连接。如果接收信号信道低于与阈值对应的电平，则每个无线电系统将给定信道检测为空信道，并且通过给定信道开始通信。当通道连接被拒绝时，每个无线电系统增加阈值。当通信开始时，每个无线电系统降低阈值。

32. 发明授权

US4747101A Method of determining optimal transmission channel in multi-station communications system 失效
标题翻译：确定多站通信系统中最优传输信道的方法
公开(公告)号：US4747101A
公开(公告)日：1988-05-24
申请号：US854961
申请日：1986-04-22
申请人： Yoshihiko Akaiwa , Yukitsuna Furuya , Kazutomo Kobayashi
发明人： Yoshihiko Akaiwa , Yukitsuna Furuya , Kazutomo Kobayashi
IPC分类号： H04B7/26 , H04L12/28 , H04L12/56 , H04W16/14 , H04W72/06 , H04Q11/00
CPC分类号： H04W72/06 , H04B7/2621 , H04L12/28 , H04W16/14 , H04W72/02 , H04W72/10
摘要： In order to effectively avoid cochannel interferences in a multi-station communications system utilizing a plurality of channels in common, the order of transmission channels to be used is determined utilizing a transmission priority assigned to each channel. The subject matter is characterized in that (a) the transmission priority of a selected channel is raised if the selected channel is not used at another station, and (b) is lowered if the selected channel is used at another station. This means that the past use records of the transmission channels are accumulated so that a good channel can be selected with high probability. In other words, a transmission channel with high priority is still ready to be used even if it was not selected in the preceding selection.
摘要翻译：为了有效地避免利用多个信道共同的多站通信系统中的同信道干扰，使用分配给每个信道的传输优先级来确定要使用的传输信道的顺序。主题的特征在于：（a）如果所选择的信道在另一个站不被使用，则提高所选信道的传输优先级，并且（b）如果所选信道在另一站使用则降低。这意味着过去使用的传输信道的记录被累积，从而可以高概率地选择好的信道。换句话说，高优先级的传输信道仍然可以被使用，即使在前面的选择中没有被选择。

33. 发明授权

US4578800A Synchronization circuit for a Viterbi decoder 失效
标题翻译：维特比解码器同步电路
公开(公告)号：US4578800A
公开(公告)日：1986-03-25
申请号：US511503
申请日：1983-07-06
申请人： Yutaka Yasuda , Yasuo Hirata , Shuji Murakami , Katsuhiro Nakamura , Yukitsuna Furuya
发明人： Yutaka Yasuda , Yasuo Hirata , Shuji Murakami , Katsuhiro Nakamura , Yukitsuna Furuya
IPC分类号： H03M13/33 , H04L7/00 , H04L7/02 , H04L7/04
CPC分类号： H03M13/33 , H04L7/0062
摘要： A Viterbi decoder synchronization circuit comprises a phase shifter for introducing a variable amount of delay time to a received bit stream of convolutional codes in response to a control signal applied thereto with respect to a word synchronization signal which is derived from the bit stream. A first detector detects maximum and minimum metric values of the Viterbi decoder. A second detector detects the difference between the detected maximum and minimum metric values for coupling to an integrator. The output of the integrator is applied to a third detector which detects when the integrator output reaches a value indicative of a word-in-sync or word-out-of-sync condition. A phase shift signal is generated in response to an output signal from the third detector and applied to the phase shifter as the control signal.
摘要翻译：维特比解码器同步电路包括一个移相器，用于响应于从比特流导出的字同步信号施加的控制信号，将可变量的延迟时间引入到所接收的卷积码比特流中。第一检测器检测维特比解码器的最大和最小度量值。第二检测器检测检测到的与积分器耦合的最大和最小度量值之间的差异。积分器的输出被施加到第三检测器，该第三检测器检测积分器输出何时达到指示同步字或字不同步条件的值。响应于来自第三检测器的输出信号产生相移信号，并将其作为控制信号施加到移相器。

34. 发明授权

US4527279A Synchronization circuit for a Viterbi decoder 失效
标题翻译：维特比解码器同步电路
公开(公告)号：US4527279A
公开(公告)日：1985-07-02
申请号：US511774
申请日：1983-07-06
申请人： Yutaka Yasuda , Yasuo Hirata , Shuji Murakami , Katsuhiro Nakamura , Yukitsuna Furuya
发明人： Yutaka Yasuda , Yasuo Hirata , Shuji Murakami , Katsuhiro Nakamura , Yukitsuna Furuya
IPC分类号： H03M13/33 , H04L7/04
CPC分类号： H03M13/33
摘要： A Viterbi decoder synchronization circuit comprises a circuit that derives a word synchronization signal from a received bit stream of convolutional codes. A first detector detects a maximum of metric values derived from the Viterbi decoder at different locations in time. A memory is provided for storing therein the address codes derived at different times and the maximum metric values detected by the first detector. A second detector is connected to the memory for detecting the presence of a path between the states addressed by the address codes stored in the memory. An integrator is connected to the second detector to integrate its output signal. To the integrator is connected a third detector which detects when the integrator output reaches a value indicative of one of word-in-sync and word-out-of-sync conditions of the Viterbi decoder. A phase shift signal is generated in response to an output signal from the third detector and applied to a phase shifter to introduce a delay time to the bit stream.
摘要翻译：维特比解码器同步电路包括从接收到的卷积码的比特流导出字同步信号的电路。第一检测器在不同的时间点检测从维特比解码器导出的度量值的最大值。提供存储器，用于在其中存储在不同时间导出的地址码和由第一检测器检测的最大度量值。第二检测器连接到存储器，用于检测由存储在存储器中的地址码寻址的状态之间的路径的存在。积分器连接到第二检测器以整合其输出信号。连接到积分器的第三检测器，其检测积分器输出何时达到表示维特比解码器的同步字和同步字的其中一个的值。响应于来自第三检测器的输出信号产生相移信号，并将其应用于移相器以向该比特流引入延迟时间。

35. 发明授权

US4367555A Digital equalizer for a cross-polarization receiver 失效
标题翻译：用于交叉极化接收机的数字均衡器
公开(公告)号：US4367555A
公开(公告)日：1983-01-04
申请号：US170640
申请日：1980-07-21
申请人： Junji Namiki , Yukitsuna Furuya
发明人： Junji Namiki , Yukitsuna Furuya
IPC分类号： H04B7/00 , H04B1/12
CPC分类号： H04B7/002
摘要： An equalizer corrects cross-polarization distortion which occurs between two series of digital signals which are transmitted on individually associated ones of two mutually orthogonal cross-polarized waves. The distortion is corrected when a circuit discriminates between the two series of digital signals and gives an output signal which represents a value judgment as to the amount of distortion which has occurred. The output signal serves as an address for selecting one of many memory element circuits, each element circuit having a predetermined value stored therein. The value stored in the selected memory element circuit is subtracted from one series of the digital signals. The idea is that, during transmission, something (e.g., raindrops) transfers energy from one to the other of the cross-polarized waves. The equalizer circuit passes judgment as to how much energy has been transferred, and then subtracts that amount of energy in order to return to the original signal. The circuit also corrects for rotation of the two mutual orthogonal waves about their common axis.
摘要翻译：均衡器校正了在两个相互正交的交叉极化波之间的相关联的两个数字信号之间发生的两个数字信号之间发生的交叉极化失真。当电路鉴别两个数字信号序列之间时，失真被校正，并给出一个输出信号，该信号代表已经发生的失真量的值判断。输出信号用作选择多个存储元件电路之一的地址，每个元件电路具有存储在其中的预定值。存储在所选存储元件电路中的值从一系列数字信号中减去。这个想法是，在传输期间，某些（例如，雨滴）将能量从一个交叉极化波中的一个传递到另一个。均衡器电路判断已经传输了多少能量，然后减去该量的能量以返回原始信号。该电路还校正了两个相互正交波绕其公共轴的旋转。

36. 发明授权

US4327440A Signal detector for use in digital communication 失效
标题翻译：用于数字通信的信号检测器
公开(公告)号：US4327440A
公开(公告)日：1982-04-27
申请号：US132482
申请日：1980-03-19
申请人： Yukitsuna Furuya , Fumio Akashi
发明人： Yukitsuna Furuya , Fumio Akashi
IPC分类号： H04B3/06 , H04L25/03 , H04L25/06 , H04L25/08 , H04L27/00 , H04L27/06 , H04L27/38 , H03K13/34
CPC分类号： H04L25/062 , H04L25/061 , H04L27/06 , H04L27/38
摘要： A signal detector for use in the digital signal communication, comprising a tentative decision means for assigning certain symbols to receiving signals based on a predetermined value; a first memory means for storing the output of said tentative decision means in sequence; a second memory means for storing a plurality of reference values prepared in association with all the signals to be received, said signals corresponding to the symbol sequence assigned by said first memory means; a selection means for selecting at least one of said reference values based on at least a part of the contents of said first memory; and a processing means wherein there is proceeded by using said selected reference value the process to relate said receiving signals with signals to be received that are most likely receiving signals among all the signals to be received, thereby producing output.
摘要翻译：一种用于数字信号通信的信号检测器，包括用于基于预定值将某些符号分配给接收信号的暂定判定装置; 用于依次存储所述暂定决定装置的输出的第一存储装置; 第二存储装置，用于存储与要接收的所有信号相关联地准备的多个参考值，所述信号对应于由所述第一存储装置分配的符号序列; 选择装置，用于基于所述第一存储器的内容的至少一部分来选择所述参考值中的至少一个; 以及处理装置，其中通过使用所述选择的参考值进行所述接收信号与要接收的所有信号中最可能接收信号的待接收信号相关联的处理，从而产生输出。

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