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31. 发明授权

US07349750B2 Method for optimizing an industrial product, system for optimizing an industrial product and method for manufacturing an industrial product 失效
公开(公告)号：US07349750B2
公开(公告)日：2008-03-25
申请号：US11480373
申请日：2006-07-05
申请人： Kazumi Nishinohara , Mitsutoshi Nakamura , Kyoichi Suguro , Koji Shirai , Ichiro Taguchi
发明人： Kazumi Nishinohara , Mitsutoshi Nakamura , Kyoichi Suguro , Koji Shirai , Ichiro Taguchi
IPC分类号： G06F19/00
CPC分类号： G05B19/41885 , G05B2219/45031 , Y02P90/20 , Y02P90/26
摘要： A method for optimizing a structure of an industrial product includes selecting control factors from among manufacturing parameters affecting a target characteristic, which is scheduled to be manufactured by a sequence of manufacturing processes; setting levels to the respective control factors; selecting a reference characteristic having a trade-off relation with the target characteristic from among characteristics of the structure; setting a reference value to the reference characteristic; selecting a prior adjustment factor affecting the reference characteristic; creating conditions for experiments assigning combinations of the levels to the respective control factors; determining an adjustment value of the prior adjustment factor so that each of characteristic values of the reference characteristic obtained by the experiments conforms substantially to the reference value; and determining experimental characteristic values of the target characteristic using the adjustment value.

32. 发明授权

US06417558B1 Semiconductor device having a reduced parasitic capacitance bonding pad structure 失效
标题翻译：具有减小的寄生电容焊盘结构的半导体器件
公开(公告)号：US06417558B1
公开(公告)日：2002-07-09
申请号：US09606147
申请日：2000-06-29
申请人： Koji Shirai
发明人： Koji Shirai
IPC分类号： H01L2701
CPC分类号： H01L24/05 , H01L23/5222 , H01L24/03 , H01L24/45 , H01L29/92 , H01L2224/02166 , H01L2224/05599 , H01L2224/45144 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01033 , H01L2924/01079 , H01L2924/10253 , H01L2924/12036 , H01L2924/14 , H01L2924/30105 , H01L2924/00 , H01L2224/48
摘要： There is provided a semiconductor device that has a reduced parasitic capacitance bonding pad structure using a silicon-on-insulator substrate. In the semiconductor device according to the present invention, a pn junction is formed by forming a semiconductor region, that has a different conductivity type from the active layer, in an active layer below a bonding pad to generate a depletion layer. Thus, a parasitic capacitance connected to the bonding pad can be reduced by a capacitance that is formed by the generation of this depletion layer. Also, a leakage current from the bonding pad can be suppressed by the generation of the pn junction.
摘要翻译：提供了使用绝缘体上硅衬底的具有减小的寄生电容结合焊盘结构的半导体器件。在根据本发明的半导体器件中，通过在接合焊盘下方的有源层中形成具有与有源层不同的导电类型的半导体区域来形成pn结，以产生耗尽层。因此，可以通过由该耗尽层的产生形成的电容来减小连接到焊盘的寄生电容。此外，可以通过pn结的产生来抑制来自接合焊盘的漏电流。

33. 发明授权

US5422505A FET having gate insulating films whose thickness is different depending on portions 失效
标题翻译： FET具有栅极绝缘膜，其厚度根据部分而不同
公开(公告)号：US5422505A
公开(公告)日：1995-06-06
申请号：US155911
申请日：1993-11-23
申请人： Koji Shirai
发明人： Koji Shirai
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L29/10 , H01L29/423
CPC分类号： H01L21/28211 , H01L21/2822 , H01L29/1045 , H01L29/42368 , H01L29/66575 , H01L29/78
摘要： A field effect transistor comprises a first conductive type semiconductor substrate, a second conductive type source region formed on the semiconductor substrate, a second conductive type drain region formed on the semiconductor substrate and non-contacting the source region, and a gate electrode formed on a channel region between the source region and the drain region through a gate insulating film, wherein the thickness of the gate insulating film is thickened at least in a two-step manner in a direction from the source region to the drain region, impurity concentration of the respective channel regions under the gate insulating film having a different film thickness is different, and impurity concentration of the channel region under the thick film portion of the gate insulating film is lower than that of the channel region under the thin film portion of the gate insulating film.
摘要翻译：场效应晶体管包括第一导电类型半导体衬底，形成在半导体衬底上的第二导电类型源极区域，形成在半导体衬底上并且不接触源极区域的第二导电型漏极区域和形成在半导体衬底上的栅电极通过栅极绝缘膜在源极区域和漏极区域之间的沟道区域，其中栅极绝缘膜的厚度至少在从源极区域到漏极区域的方向上以两级方式增厚，具有不同膜厚度的栅极绝缘膜下面的各个沟道区域是不同的，并且栅极绝缘膜的厚膜部分下面的沟道区域的杂质浓度低于栅极绝缘膜的薄膜部分下面的沟道区域的杂质浓度电影。

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