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31. 发明申请

US20060006459A1 Semiconductor system functioning as thyristor in on-state, and as bipolar transistor in transient state or with overcurrent 有权
标题翻译：半导体系统作为晶闸管处于导通状态，并且作为双极晶体管处于瞬态或过电流
公开(公告)号：US20060006459A1
公开(公告)日：2006-01-12
申请号：US11170064
申请日：2005-06-30
申请人： Koh Yoshikawa
发明人： Koh Yoshikawa
IPC分类号： H01L29/76
CPC分类号： H01L29/7404 , H01L27/0629 , H01L29/7397 , H01L29/87 , H01L2224/48091 , H01L2224/4813 , H01L2224/48137 , H01L2224/49111 , H01L2224/49175 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor system includes a self arc-extinguishing device, and an IGBT that works as a thyristor when a current between a first terminal and a second terminal connected to a second well electrode is small, and as a bipolar transistor when that current is large, and automatically switches between them according to the magnitude of the current. The IGBT is formed with a first conductivity-type semiconductor substrate. On a surface layer of the substrate is a second conductivity-type well region to which a first well electrode is connected. A first conductivity-type emitter region, to which an emitter electrode is connected, is disposed on a surface layer in the well region. A control electrode is disposed through an insulating film partially covering the well and emitter regions. A second conductivity-type well layer, to which the second well electrode is connected, is disposed on a back surface side of the substrate. The self arc-extinguishing device is connected to the IGBT between the emitter electrode and the first terminal. The rectifying device is connected between the first well electrode and the first terminal.
摘要翻译：半导体系统包括自熄灭装置，以及当连接到第二阱电极的第一端子和第二端子之间的电流小时用作晶闸管的IGBT，当该电流较大时，作为双极型晶体管，并根据电流的大小自动在它们之间切换。 IGBT由第一导电型半导体基板形成。在基板的表面层上是与第一阱电极连接的第二导电型阱区。连接发射电极的第一导电型发射极区域设置在阱区的表面层上。控制电极通过部分地覆盖阱和发射极区域的绝缘膜设置。在第二阱电极连接的第二导电型阱层设置在衬底的背面侧。自熄灭装置与发射电极和第一端子之间的IGBT连接。整流装置连接在第一阱电极和第一端子之间。

32. 发明授权

US08604584B2 Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08604584B2
公开(公告)日：2013-12-10
申请号：US13038349
申请日：2011-03-01
申请人： Hiroki Wakimoto , Kenichi Iguchi , Koh Yoshikawa , Tsunehiro Nakajima , Shunsuke Tanaka , Masaaki Ogino
发明人： Hiroki Wakimoto , Kenichi Iguchi , Koh Yoshikawa , Tsunehiro Nakajima , Shunsuke Tanaka , Masaaki Ogino
IPC分类号： H01L21/78 , H01L21/302
CPC分类号： H01L21/308 , H01L21/302 , H01L21/78 , H01L29/06
摘要： Some embodiments of the present invention relate to a semiconductor device and a method of manufacturing a semiconductor device capable of preventing the deterioration of electrical characteristics. A p-type collector region is provided on a surface layer of a backside surface of an n-type drift region. A p+-type isolation layer for obtaining reverse blocking capability is provided at the end of an element. In addition, a concave portion is provided so as to extend from the backside surface of the n-type drift region to the p+-type isolation layer. A p-type region is provided and is electrically connected to the p+-type isolation layer. The p+-type isolation layer is provided so as to include a cleavage plane having the boundary between the bottom and the side wall of the concave portion as one side.
摘要翻译：本发明的一些实施例涉及能够防止电特性劣化的半导体器件和半导体器件的制造方法。 p型集电极区域设置在n型漂移区域的背面的表面层上。在元件的末端提供了用于获得反向阻挡能力的p +型隔离层。此外，设置从n型漂移区的背面向p +型隔离层延伸的凹部。提供p型区域并且电连接到p +型隔离层。提供p +型隔离层，以便包括具有作为一侧的凹部的底部和侧壁之间的边界的解理面。

33. 发明授权

US08558342B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08558342B2
公开(公告)日：2013-10-15
申请号：US12892676
申请日：2010-09-28
申请人： Koh Yoshikawa , Motoyoshi Kubouchi
发明人： Koh Yoshikawa , Motoyoshi Kubouchi
IPC分类号： H01L29/02
CPC分类号： H01L29/7393 , H01L29/0619 , H01L29/404 , H01L29/7395
摘要： A reverse blocking IGBT according to the invention can include a reverse breakdown withstanding region, p-type outer field limiting rings formed in a reverse breakdown withstanding region and an outer field plate connected to the outer field limiting rings, the outer field plate including a first outer field plate in contact with outer field limiting rings nearest to the active region and second outer field plates in contact with other outer field limiting rings. The first outer field plate having an active region side edge portion projecting toward the active region and second outer field plate having an edge area side edge portion projecting toward the edge area. The reverse blocking IGBT according to the invention can facilitate improving the withstand voltages thereof and reducing the area thereof.
摘要翻译：根据本发明的反向阻断IGBT可以包括反向击穿承受区域，形成在反向击穿区域中的p型外部场限制环和连接到外部场地限制环的外部场板，外部场板包括第一外场板与最靠近有源区的外场限界环接触，而第二外场板与其它外场限制环接触。第一外场板具有朝向有源区域突出的有源区域侧边缘部分和第二外部场板，其具有朝向边缘区域突出的边缘区域侧边缘部分。根据本发明的反向阻断IGBT可以有助于提高其耐受电压并减小其面积。

34. 发明申请

US20130001638A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130001638A1
公开(公告)日：2013-01-03
申请号：US13583666
申请日：2011-10-19
申请人： Koh Yoshikawa
发明人： Koh Yoshikawa
IPC分类号： H01L29/739
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/0865 , H01L29/0869 , H01L29/1095 , H01L29/66734 , H01L29/7397
摘要： Plural gate trenches are formed in the surface of an n-type drift region. A gate electrode is formed across a gate oxide film on the inner walls of the gate trenches. P-type base regions are selectively formed so as to neighbor each other in the gate trench longitudinal direction between neighboring gate trenches. An n-type emitter region is formed in contact with the gate trench in a surface layer of the p-type base regions. Also, a p-type contact region with a concentration higher than that of the p-type base region is formed in the surface layer of the p-type base region so as to be in contact with the gate trench side of the n-type emitter region. An edge portion on the gate trench side of the n-type emitter region terminates inside the p-type contact region.
摘要翻译：多个栅极沟槽形成在n型漂移区域的表面。在栅极沟槽的内壁上的栅氧化膜上形成栅电极。选择性地形成P型基区，以便在相邻栅极沟槽之间的栅极沟槽纵向方向上彼此相邻。 n型发射极区域形成为与p型基极区域的表面层中的栅极沟槽接触。此外，在p型基极区域的表面层中形成浓度高于p型基极区域的p型接触区域，以与n型基极区域的栅极沟道侧接触发射区。 n型发射极区域的栅极沟槽侧的边缘部分终止在p型接触区域的内部。

35. 发明授权

US08278682B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08278682B2
公开(公告)日：2012-10-02
申请号：US13116650
申请日：2011-05-26
申请人： Koh Yoshikawa , Kenichi Iguchi
发明人： Koh Yoshikawa , Kenichi Iguchi
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： H01L29/7395 , H01L29/0619 , H01L29/404
摘要： A semiconductor device that has a reduced size and exhibits a superior blocking voltage capability. A semiconductor device includes an edge termination structure between an active region and an isolation region, the edge termination structure being composed of an edge termination structure for a forward bias section and an edge termination structure for a reverse bias section. A plurality of field limiting rings (FLRs) and a plurality of field plates (FPs) are provided in the edge termination structure for the forward bias section and the edge termination structure for the reverse bias section. A first forward FP that is the nearest of the plurality of FPs to the edge termination structure for the reverse bias section is formed to extend towards the isolation region side. A first reverse FP that is the nearest of the plurality of FPs to the edge termination structure for the forward bias section is formed to extend towards the active region side. The first reverse FP stops the depletion layer expanding from the active region on application of a forward voltage. The first forward FP stops the depletion layer expanding from the isolation region on application of a reverse voltage.
摘要翻译：具有减小的尺寸并且具有优异的阻挡电压能力的半导体器件。半导体器件包括在有源区和隔离区之间的边缘终端结构，边缘终端结构由用于正偏压部分的边缘终端结构和用于反向偏压部分的边缘终端结构组成。在用于正偏压部分的边缘终端结构和用于反向偏压部分的边缘终端结构中，设置有多个场限制环（FLR）和多个场板（FP）。形成朝向隔离区域侧延伸到与反向偏置部分的边缘终端结构相邻的多个FP中的最近的第一前向FP。形成朝向偏置部分的边缘终端结构的多个FP中最接近的第一反向FP朝向有源区域侧延伸。第一反向FP在施加正向电压时停止从有源区扩展的耗尽层。第一个前向FP在施加反向电压时停止从隔离区扩展的耗尽层。

36. 发明授权

US08242556B2 Vertical and trench type insulated gate MOS semiconductor device 有权
标题翻译：垂直和沟槽型绝缘栅MOS半导体器件
公开(公告)号：US08242556B2
公开(公告)日：2012-08-14
申请号：US12767356
申请日：2010-04-26
申请人： Koh Yoshikawa , Hiroki Wakimoto , Masahito Otsuki
发明人： Koh Yoshikawa , Hiroki Wakimoto , Masahito Otsuki
IPC分类号： H01L29/76
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/66348
摘要： A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.
摘要翻译：提供一种垂直和沟槽型绝缘栅极MOS半导体器件，其中p型沟道区域的表面和n型半导体衬底的部分表面在沟槽纵向方向上交替排列成平行布置，并且选择性地形成在p型沟道区域的表面上的n +型发射极区域在沟槽侧面较宽，并且朝向沟槽之间的中心点变窄。这使得器件能够实现低导通电阻和增强的关断能力。

37. 发明授权

US07943439B2 Method for manufacturing semiconductor apparatus 有权
标题翻译：半导体装置的制造方法
公开(公告)号：US07943439B2
公开(公告)日：2011-05-17
申请号：US12470658
申请日：2009-05-22
申请人： Koh Yoshikawa
发明人： Koh Yoshikawa
IPC分类号： H01L21/332
CPC分类号： H01L27/0664 , H01L27/0248 , H01L29/0839 , H01L29/2003 , H01L29/66204 , H01L29/66348 , H01L29/7397
摘要： A manufacturing method is provided for manufacturing a semiconductor apparatus including a main semiconductor device and a subsidiary semiconductor device, which facilitates preventing characteristics variations from causing and reducing the manufacturing costs. The method includes forming p-type well region in the surface portion of single-crystal semiconductor substrate of a main semiconductor device, mounting a single-crystal silicon diode above p-type well region with an insulator film interposed between diode and p-type well region for forming subsidiary semiconductor device, forming an insulator film on the main semiconductor device such that single-crystal silicon diode is covered with insulator film for fixing single-crystal silicon diode to single-crystal semiconductor substrate, and forming a metal film on the main semiconductor device for further forming a cathode side wiring on n-type cathode region in single-crystal silicon diode and an anode side wiring on p-type anode region in single-crystal silicon diode.
摘要翻译：提供一种用于制造包括主半导体器件和辅助半导体器件的半导体器件的制造方法，其有助于防止特性变化引起和降低制造成本。该方法包括在主半导体器件的单晶半导体衬底的表面部分中形成p型阱区，在p型阱区上方安装单晶硅二极管，其中介于二极管和p型阱之间的绝缘膜形成辅助半导体器件的区域，在主半导体器件上形成绝缘膜，使得单晶硅二极管覆盖有用于将单晶硅二极管固定在单晶半导体衬底上的绝缘膜，并在主体上形成金属膜用于在单晶硅二极管的n型阴极区域进一步形成阴极侧布线的半导体器件和单晶硅二极管中p型阳极区域上的阳极侧布线。

38. 发明授权

US07772677B2 Semiconductor device and method of forming the same having a junction termination structure with a beveled sidewall 有权
标题翻译：半导体器件及其形成方法，具有具有斜面侧壁的接合端接结构
公开(公告)号：US07772677B2
公开(公告)日：2010-08-10
申请号：US11670419
申请日：2007-02-02
申请人： Koh Yoshikawa
发明人： Koh Yoshikawa
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66712 , H01L29/0615 , H01L29/0634 , H01L29/0661 , H01L29/402 , H01L29/41741 , H01L29/6609 , H01L29/7811 , H01L29/868
摘要： A semiconductor device has a semiconductor substrate including an n-type high impurity concentration layer inhibiting a depletion layer from spreading, an n-type low impurity concentration drift layer, and a p-type high impurity concentration layer forming a p-n main junction between the drift layer. In the active region, an effective current flows in the direction of the thickness of the substrate. The device has an inclined trench that cuts the p-n main junction at a positive bevel angle from the semiconductor substrate surface on the side of the n-type high impurity concentration layer to penetrate through the substrate for separating it into chips. In the device, along the sidewall of the inclined trench in the n-type drift layer, an n-type surface region is formed with an impurity concentration lower than that in the n-type drift layer.
摘要翻译：半导体器件具有包括抑制耗尽层扩散的n型高杂质浓度层的半导体衬底，n型低杂质浓度漂移层和在漂移之间形成pn主结的p型高杂质浓度层层。在有源区域中，有效电流在衬底的厚度方向上流动。该器件具有倾斜的沟槽，其以正斜面角度从n型高杂质浓度层侧的半导体衬底表面切割p-n主结，以穿透衬底以将其分离成芯片。在器件中，沿着n型漂移层中的倾斜沟槽的侧壁，形成杂质浓度低于n型漂移层中的杂质浓度的n型表面区域。

39. 发明申请

US20090315070A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090315070A1
公开(公告)日：2009-12-24
申请号：US12466909
申请日：2009-05-15
申请人： Koh Yoshikawa
发明人： Koh Yoshikawa
IPC分类号： H01L29/739
CPC分类号： H01L29/7397 , H01L29/0634 , H01L29/0834 , H01L29/66333 , H01L29/66348 , H01L29/7395
摘要： A power semiconductor device is provided, that realizes high-speed turnoff and soft switching at the same time, includes n-type main semiconductor layer including lightly doped n-type semiconductor layer and extremely lightly doped n-type semiconductor layer arranged alternately and repeatedly between p-type channel layer and field stop layer and in parallel to the first major surface of n-type main semiconductor layer. Extremely lightly doped n-type semiconductor layer is doped more lightly than lightly doped n-type semiconductor layer. Lightly doped n-type semiconductor layer prevents a space charge region from expanding at the time of turnoff. Extremely lightly doped n-type semiconductor layer expands the space charge region at the time of turnoff to eject electrons and holes quickly further to realize high-speed turnoff. The pattern of arrangement of the lightly doped n-type semiconductor layer and extremely lightly doped n-type semiconductor layer is independent of the arrangement pattern of the gate electrode structure.
摘要翻译：提供了一种同时实现高速关断和软开关的功率半导体器件，包括n型主半导体层，其包括轻掺杂的n型半导体层和极轻掺杂的n型半导体层， p型沟道层和场阻挡层，并且与n型主半导体层的第一主表面平行。非常轻掺杂的n型半导体层比轻掺杂的n型半导体层更轻掺杂。轻掺杂的n型半导体层防止空位电荷区域在断电时膨胀。极轻掺杂的n型半导体层在断电时扩展空间电荷区域，从而快速地进一步喷射电子和空穴，以实现高速关断。轻掺杂的n型半导体层和极轻掺杂的n型半导体层的排列方式与栅电极结构的配置图形无关。

40. 发明授权

US07535059B2 Semiconductor device and manufacturing method of the semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07535059B2
公开(公告)日：2009-05-19
申请号：US11564053
申请日：2006-11-28
申请人： Koh Yoshikawa , Akio Sugi , Kouta Takahashi , Manabu Takei , Haruo Nakazawa , Noriyuki Iwamuro
发明人： Koh Yoshikawa , Akio Sugi , Kouta Takahashi , Manabu Takei , Haruo Nakazawa , Noriyuki Iwamuro
IPC分类号： H01L29/76
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/4236 , H01L29/66734 , H01L29/7802 , H01L29/7813
摘要： A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.
摘要翻译：公开了一种包括n型半导体衬底，p型沟道区和设置在n型半导体衬底和p型沟道区之间的结层的半导体器件。接合层具有与n型半导体衬底的主表面平行的方向交替布置的n型漂移区和p型隔离区。形成结层的p型分隔区的杂质浓度比n型漂移区高。这使得半导体器件具有增强的击穿电压，并且同时具有降低的导通电阻。

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