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31. 发明授权

US6134064A Playback clock extracting apparatus 失效
标题翻译：播放时钟提取装置
公开(公告)号：US6134064A
公开(公告)日：2000-10-17
申请号：US80385
申请日：1998-05-18
申请人： Masafumi Sato , Kiyokazu Hashimoto , Masato Izawa
发明人： Masafumi Sato , Kiyokazu Hashimoto , Masato Izawa
IPC分类号： G11B5/008 , G11B5/09 , G11B20/10 , G11B20/14 , H03L7/091
CPC分类号： G11B20/10037 , G11B20/10009 , G11B20/1403 , H03L7/091 , G11B5/00813 , G11B5/09
摘要： A playback clock extracting device having: a quantization member for quantizing, at a sampling clock rate having a rate twice a recording rate, a signal played back from a recording medium so as to output sample data, a digital equalizer for subjecting the sample data to digital equalization so as to alternately output playback data and PLL data at an interval of one sampling clock, cycle a ternary decision member for making a ternary decision as to whether the playback data is positive, zero or negative. The playback clock extracting device further having arithmetic unit for calculating a sampling phase error in the quantization member by multiplying a result of the decision of the ternary decision member by a difference between two successive data values of the PLL data outputted immediately prior to and immediately after the playback data for the decision of the ternary decision member, respectively, a sampling clock generating member which controls a phase and an oscillation frequency on the basis of the sampling phase error outputted by the arithmetic unit so as to generate the sampling clock, and a playback clock generating member which divides a frequency of the sampling clock by two so as to generate a playback clock for detecting the playback data.
摘要翻译：一种重放时钟提取装置，具有：量化部件，用于以具有两倍于记录速率的速率的采样时钟速率对从记录介质播放的信号进行量化，以输出采样数据;数字均衡器，用于使样本数据数字均衡，以便以一个采样时钟的间隔交替地输出重放数据和PLL数据，循环一个三进制决策构件，用于作出关于重放数据是正的还是负的否定的三元决定。重放时钟提取装置还具有运算单元，用于通过将三进制判定构件的判定结果乘以在紧接在之前和之后输出的PLL数据的两个连续数据值之间的差来计算量化构件中的采样相位误差分别用于三进制判定器的判定的重放数据，采样时钟产生部件，其基于由运算器输出的采样相位误差来控制相位和振荡频率，以产生采样时钟;以及将采样时钟的频率除以2的再现时钟产生部件，以便产生用于检测重放数据的重放时钟。

32. 发明授权

US6125074A Semiconductor memory device having a small memory cell driving circuit 失效
标题翻译：具有小存储单元驱动电路的半导体存储器件
公开(公告)号：US6125074A
公开(公告)日：2000-09-26
申请号：US855889
申请日：1997-05-12
申请人： Nobuo Murakami , Kiyokazu Hashimoto
发明人： Nobuo Murakami , Kiyokazu Hashimoto
IPC分类号： G11C11/413 , G11C8/08 , G11C11/407 , G11C16/06 , G11C17/18 , G11C8/10
CPC分类号： G11C8/08
摘要： In a semiconductor memory device including memory cells, first and second decoders generate first and second selection signals, and a driver circuit generates a drive signal for driving the memory cells. The driver circuit includes a transfer gate, controlled by the first selection signal, thus passing the second selection signal to generate the drive signal.
摘要翻译：在包括存储单元的半导体存储器件中，第一和第二解码器产生第一和第二选择信号，驱动电路产生用于驱动存储单元的驱动信号。驱动器电路包括由第一选择信号控制的传输门，从而传递第二选择信号以产生驱动信号。

33. 发明授权

US5889716A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5889716A
公开(公告)日：1999-03-30
申请号：US16274
申请日：1998-01-30
申请人： Kiyokazu Hashimoto
发明人： Kiyokazu Hashimoto
IPC分类号： G11C16/02 , G11C11/56 , G11C16/06 , G11C7/02 , G11C7/00 , G11C8/00
CPC分类号： G11C11/5642 , G11C11/5621 , G11C16/32 , G11C2211/5634 , G11C2211/5642 , G11C7/06
摘要： In a semiconductor memory storing multivalue information, a sense section includes a first latch receiving an output of a first differential amplifier in a sense amplifier, a second latch receiving an output of a second differential amplifier in the sense amplifier and an output of the first latch, and a third latch receiving an output of a third differential amplifier in the sense amplifier and an output of the second latch. When a selected memory cell has the lowest threshold, the output of the first latch becomes a low level, and correspondingly, the output of the second latch is forcibly brought to the low level in response to the low level of the output of the first latch, and then, the output of the third latch is forcibly brought to the low level in response to the low level of the output of the second latch. Therefore, even if the output of the second and third differential amplifiers varies because of power supply voltage noises, the data can be correctly read out without being influenced by the power supply voltage noises.
摘要翻译：在存储多值信息的半导体存储器中，感测部分包括接收读出放大器中的第一差分放大器的输出的第一锁存器，接收读出放大器中的第二差分放大器的输出的第二锁存器和第一锁存器的输出以及第三锁存器，其接收读出放大器中的第三差分放大器的输出和第二锁存器的输出。当所选择的存储单元具有最低阈值时，第一锁存器的输出变为低电平，并且相应地，响应于第一锁存器的输出的低电平，第二锁存器的输出被强制地变为低电平然后，响应于第二锁存器的输出的低电平，第三锁存器的输出被强制地变为低电平。因此，即使由于电源电压噪声而导致第二和第三差分放大器的输出变化，所以可以在不受电源电压噪声影响的情况下正确读出数据。

34. 发明授权

US5293333A Non-volatile semiconductor memory device equipped with high-speed sense amplifier unit 失效
标题翻译：配有高速读出放大器单元的非易失性半导体存储器件
公开(公告)号：US5293333A
公开(公告)日：1994-03-08
申请号：US744216
申请日：1991-10-09
申请人： Kiyokazu Hashimoto
发明人： Kiyokazu Hashimoto
IPC分类号： G11C17/00 , G11C16/06 , G11C16/26 , G11C11/40
CPC分类号： G11C16/26
摘要： An electrically erasable and programmable read only memory device has a sense amplifier circuit for changing an output voltage level at the output node thereof indicative of either an erased or a write-in state of a memory cell to be accessed, and the output voltage level is compared with a reference voltage level so as to see whether the output voltage is indicative of the erased state or the write-in state, wherein the sense amplifier circuit is associated with a current make-up circuit for compensating the current to the output node of the sense amplifier circuit so that the output voltage level rapidly reaches a high or low voltage level regardless of fluctuation of the reference voltage level.
摘要翻译：电可擦除可编程只读存储器件具有用于改变其输出节点处的输出电压电平的读出放大器电路，其指示要访问的存储器单元的擦除状态或写入状态，并且输出电压电平为与参考电压电平相比，以便看出输出电压是指示擦除状态还是写入状态，其中读出放大器电路与用于补偿到输出节点的电流的电流补偿电路相关联读出放大器电路，使得无论参考电压电平的波动如何，输出电压电平快速达到高或低电压电平。

35. 发明授权

US5214606A Non-volatile semiconductor memory and method for driving the same 失效
标题翻译：非易失性半导体存储器及其驱动方法
公开(公告)号：US5214606A
公开(公告)日：1993-05-25
申请号：US731335
申请日：1991-07-17
申请人： Kiyokazu Hashimoto
发明人： Kiyokazu Hashimoto
IPC分类号： G11C17/00 , G11C16/06 , G11C16/08 , G11C16/12 , G11C16/16 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/08 , G11C16/12 , G11C16/16
摘要： In a flash type EEPROM comprising a memory cell matrix, an X decoder and a Y decoder, the X decoder includes a first circuit for charging an output of the first circuit to a voltage supply voltage when the first circuit is selected by an address signal, a depletion N-channel MOS transistor connected between the output node of the first circuit and a corresponding word line and having a gate connected to receive a control voltage, a second circuit for generating a high voltage at an output node of the second circuit at the time of a write mode, and a enhancement P-channel MOS transistor connected between the output node of the second circuit and the corresponding word line and having a gate connected to receive an erase verify signal. In an erase voltage verify mode, the gate of the depletion N-channel transistor is brought to a low level and the enhancement P-channel MOS transistor is turned off, so that a selected word lines is charged through the depletion N-channel MOS transistor. Accordingly, a voltage of the selected word line is set to a level lower than the voltage supply voltage.
摘要翻译：在包括存储单元矩阵，X解码器和Y解码器的闪速型EEPROM中，X解码器包括用于通过地址信号选择第一电路时将第一电路的输出充电到电压电源电压的第一电路，连接在第一电路的输出节点与对应的字线之间并具有连接以接收控制电压的栅极的耗尽型N沟道MOS晶体管，用于在第二电路的输出节点处产生高电压的第二电路，连接在第二电路的输出节点和对应的字线之间并具有连接以接收擦除验证信号的栅极的增强型P沟道MOS晶体管。在擦除电压验证模式中，耗尽型N沟道晶体管的栅极变为低电平，并且增强型P沟道MOS晶体管截止，使得所选择的字线通过耗尽型N沟道MOS晶体管。因此，所选字线的电压被设定为低于电源电压的电平。

36. 发明授权

US5008566A Power supply voltage drop detection circuit for use in EEPROM memory 失效
标题翻译：用于EEPROM存储器的电源电压降检测电路
公开(公告)号：US5008566A
公开(公告)日：1991-04-16
申请号：US444505
申请日：1989-11-30
申请人： Kiyokazu Hashimoto
发明人： Kiyokazu Hashimoto
IPC分类号： G11C17/00 , G11C5/14 , G11C16/02 , G11C16/06 , G11C16/30 , H03K17/22
CPC分类号： G11C16/30 , G11C5/143 , H03K17/223
摘要： A power supply voltage drop detection circuit has first and second N-channel field-effect-transistors. The drain of the first N-channel FET is connected to a power supply voltage line and its gate to ground. The drain of the second N-channel FET connected to the source of the first N-channel FET and its source is connected to the ground. A control voltage to the gate of the second N-channel FET maintains the second N-channel FET conducting. A P-channel field-effect-transistor has its source connected to the power supply voltage line and its gate connected to a connection node between the first and second N-channel field-effect-transistors. A third N-channel FET has its drain connected to the drain of the P-channel FET and its source connected to the ground. The gate of the third N-channel FET receives a controlled gate voltage which maintains the third N-channel FET conducting. An inverter has its input connected to a node between the P-channel FET and the third N-channel FET. The inverter output generates a signal indicative of the power supply voltage drop.
摘要翻译：电源电压降检测电路具有第一和第二N沟道场效应晶体管。第一N沟道FET的漏极连接到电源电压线，并将其栅极接地。连接到第一N沟道FET的源极及其源极的第二N沟道FET的漏极连接到地。到第二N沟道FET的栅极的控制电压保持第二N沟道FET导通。 P沟道场效应晶体管的源极连接到电源电压线，其栅极连接到第一和第二N沟道场效应晶体管之间的连接节点。第三个N沟道FET的漏极连接到P沟道FET的漏极，其源极连接到地。第三N沟道FET的栅极接收保持第三N沟道FET导通的受控栅极电压。反相器的输入连接到P沟道FET和第三N沟道FET之间的节点。逆变器输出产生指示电源电压降的信号。

37. 发明授权

US4878220A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4878220A
公开(公告)日：1989-10-31
申请号：US123008
申请日：1987-11-19
申请人： Kiyokazu Hashimoto
发明人： Kiyokazu Hashimoto
IPC分类号： G06F12/16 , G06F11/10 , G06F11/267 , G11C29/00 , G11C29/02 , G11C29/36 , G11C29/42
CPC分类号： G06F11/2215 , G06F11/1008 , G06F11/1076 , G11C29/02 , G11C29/36
摘要： For sufficient diagnostic operation, there is disclosed a semiconductor memory device having a write-in mode, a read-out mode and a diagnostic mode. The seminconductor memory device includes: (a) a check-bit producing circuit operative to produce check-bits based on data bits of a piece of data information supplied from the outside thereof in the write-in mode; (b) a plurality of memory cell groups each capable of storing the data bits of the piece of data information and the check bits produced by the check-bit producing circuit; (c) an error detecting circuit operative to identify at least one error bit opposite in logic level from the corresponding data bit on the basis of the piece of data information stored in the memory cell group and to produce an output signal consisting of a plurality of data bits and representing the error bitm, if any, in the read-out mode or the diagnostic mode; (d) an error correction circuit supplied with the data bits of the piece of data information stored in the memory cell group and the output signal produced by the error detecting circuit and operative to change the error data bit to the corresponding data bit in the read-out mode or the diagnostic mode; and (e) a test pattern producing circuit operative to produce dummy bits having an error data bit and check bits produced on the basis of the data bits without the error data bit and supplying the dummy bits to the error detecting circuit in the diagnostic mode, so that the diagnostic operations can be achieved for both of the error detecting circuit and the error correction circuit.
摘要翻译：为了充分的诊断操作，公开了具有写入模式，读出模式和诊断模式的半导体存储器件。半导体存储器件包括：（a）校验位产生电路，用于基于从写入模式从其外部提供的一条数据信息的数据位产生校验位; （b）多个存储单元组，每个存储单元组能够存储由该校验位产生电路产生的数据信息和校验位的数据位; （c）错误检测电路，其操作以基于存储在存储单元组中的数据信息来识别逻辑电平与逻辑电平相反的至少一个误差位，并产生由多个数据位，并在读出模式或诊断模式下表示误差位（如果有）; （d）误差校正电路，其被提供有存储在存储单元组中的数据信息的数据位和由误差检测电路产生的输出信号，并可操作以将误差数据位改变为读出的相应数据位出模式或诊断模式; 以及（e）测试模式产生电路，用于产生具有错误数据位和基于没有误差数据位的数据位产生的校验位的虚拟位，并在诊断模式下将错误位提供给错误检测电路，从而可以对误差检测电路和误差校正电路两者进行诊断。

38. 发明授权

US4658156A Voltage detection circuit for detecting input voltage larger in absolute value than power supply voltage 失效
标题翻译：用于检测绝对值大于电源电压的输入电压的电压检测电路
公开(公告)号：US4658156A
公开(公告)日：1987-04-14
申请号：US679450
申请日：1984-12-07
申请人： Kiyokazu Hashimoto
发明人： Kiyokazu Hashimoto
IPC分类号： G11C29/00 , G01R19/165 , G11C5/14 , G11C16/06 , G11C16/30 , G11C17/00 , G11C29/14 , H03K17/30 , H03K19/20 , H03K5/153 , G01R31/28 , G11C8/00
CPC分类号： H03K17/302 , G01R19/16519 , G11C16/30 , G11C5/143
摘要： A voltage detection circuit for detecting an input voltage larger in absolute value than a power supply voltage is disclosed. This circuit comprises a first transistor connected between a terminal supplied with the input voltage and a circuit node, and a second and a third complementary transistors connected in series between the circuit node and a reference potential terminal. The first transistor is used as a voltage-dropping means, and the gates of the second and third transistors are commonly supplied with the power supply voltage. When the potential difference between the circuit node and the gate of the second transistor exceeds the threshold value of the same transistor, the second transistor is turned ON and the potential at the connection point of the second and third transistors begins to change. At this time, the input voltage is higher in absolute value than the power supply voltage because the first transistor operates as the voltage-dropping means.
摘要翻译：公开了一种用于检测绝对值大于电源电压的输入电压的电压检测电路。该电路包括连接在提供有输入电压的端子和电路节点之间的第一晶体管和串联连接在电路节点和参考电位端子之间的第二和第三互补晶体管。第一晶体管用作降压装置，第二和第三晶体管的栅极通常被供给电源电压。当电路节点和第二晶体管的栅极之间的电位差超过同一晶体管的阈值时，第二晶体管导通，第二和第三晶体管的连接点处的电位开始变化。此时，由于第一晶体管作为降压装置工作，所以输入电压的绝对值高于电源电压。

39. 发明授权

US4492988A Dropout compensation system 失效
标题翻译：压差补偿系统
公开(公告)号：US4492988A
公开(公告)日：1985-01-08
申请号：US411265
申请日：1982-08-25
申请人： Kiyokazu Hashimoto , Keizi Hayashi
发明人： Kiyokazu Hashimoto , Keizi Hayashi
IPC分类号： G11B20/06 , G11B20/18 , H04N5/94 , H04N5/95 , H04N5/76
CPC分类号： H04N5/95 , G11B20/18 , H04N5/94
摘要： A dropout compensation system used with a video tape recorder, video disc, etc. is disclosed. In conventional modulation systems, a reproduced signal which has been modulated in a modulation system in which the signal information is determined by the zero passage of the carrier, is delayed in the form of the modulated signal, and if a dropout occurs, the reproduced signal is switched to the delayed signal by a first switch thereby to compensate for the dropout. The phase of the modulated signal becomes discontinuous each time the switch is operated, thus causing an offensive spark-like interference upon demodulation. The invention is intended for reducing these noises and comprises a second demodulator for normally demodulating the delayed signal and a second switch operated at a different timing from the first switch in response to the dropout. The noise is extracted by the operation of the second switch and the extracted noise is cancelled by being combined at opposite polarity with the demodulated reproduced signal, which signal contains the noise but has been compensated for the dropout. A noise-removing circuit utilizing the horizontal correlation of the TV signal may be easily added to the configuration of the present invention.
摘要翻译：公开了一种与磁带录像机，视频盘等一起使用的压差补偿系统。在传统的调制系统中，在调制方式中被调制的信号由载波的零通道确定的再生信号以调制信号的形式被延迟，如果发生了压差，则再生信号通过第一开关切换到延迟信号，从而补偿掉落。调制信号的相位在每次开关操作时变得不连续，从而在解调时产生令人反感的火花状干扰。本发明旨在减少这些噪声，并且包括用于正常解调延迟信号的第二解调器和响应于该丢失在与第一开关不同的定时操作的第二开关。通过第二开关的操作提取噪声，并且通过与解调的再现信号相反的极性组合提取的噪声被消除，该信号包含噪声但是已被补偿。利用TV信号的水平相关性的噪声去除电路可以容易地添加到本发明的配置中。

40. 发明授权

US08642715B2 Polyester film and method for producing same, backsheet for solar cell, and solar cell module 有权
标题翻译：聚酯薄膜及其制造方法，太阳能电池用底片和太阳能电池组件
公开(公告)号：US08642715B2
公开(公告)日：2014-02-04
申请号：US13158143
申请日：2011-06-10
申请人： Kiyokazu Hashimoto , Yasutomo Goto , Kenji Kano
发明人： Kiyokazu Hashimoto , Yasutomo Goto , Kenji Kano
IPC分类号： B32B27/36 , C08G63/02 , C08G63/12 , C08G63/127 , C08G63/16 , C08G63/18 , C08G63/181 , C08G63/183
CPC分类号： C08J5/18 , C08J7/08 , C08J2367/02 , H01L31/049 , Y02E10/50 , Y10T428/31786
摘要： A polyester film containing a polyester resin having an intrinsic viscosity IV of from 0.73 to 0.9 dL/g in which the polyester film has a specific heat change at 85° C. to 135° C. (ΔCp) of from 0.06 to 0.1 J/g, has an excellent weather resistance, a good planar surface state and a low thermal shrinkage.
摘要翻译：一种聚酯膜，其特征粘度IV为0.73〜0.9dL / g的聚酯树脂，其中聚酯膜的85℃〜135℃的比热变化率（ΔCp）为0.06〜0.1J / g具有优异的耐候性，良好的平面状态和低的热收缩率。

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