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    • 35. 发明授权
    • High-performance pipelined central processor for predicting the
occurrence of executing single-cycle instructions and multicycle
instructions
    • 高性能流水线中央处理器,用于预测执行单周期指令和多周期指令的发生
    • US5136696A
    • 1992-08-04
    • US211977
    • 1988-06-27
    • Robert F. BeckwithNeil J. JohnsonSuren IrukullaSteven SchwartzNihar Mohapatra
    • Robert F. BeckwithNeil J. JohnsonSuren IrukullaSteven SchwartzNihar Mohapatra
    • G06F9/38G06F9/42
    • G06F9/3806G06F9/4426
    • A pipelined central processor capable of executing both single-cycle instructions and multicycle instructions is provided. An instruction fetch stage of the processor includes an instruction cache memory and a prediction cache memory that are commonly addressed by a program counter register. The instruction cache memory stores instructions of a program being executed and microinstructions of a multicycle instruction interpreter. The prediction cache memory stores interpreter call predictions and interpreter entry addresses at the addresses of the multicycle intructions. When a call prediction occurs, the entry address of the instruction interpreter is loaded into the program counter register on the processing cycle immediately following the call prediction, and a return address is pushed onto a stack. The microinstructions of the interpreter are fetched sequentially from the instruction cache memory. When the interpreter is completed, the prediction cache memory makes a return prediction. The return address is transferred from the stack to the program counter register on the processing cycle immediately following the return prediction, and normal program flow is resumed. The prediction cache memory also stores branch instruction predictions and branch target addresses.
    • 提供了能够执行单周期指令和多周期指令的流水线中央处理器。 处理器的指令提取级包括由程序计数器寄存器共同寻址的指令高速缓冲存储器和预测高速缓存存储器。 指令高速缓存存储器存储正在执行的程序的指令和多周期指令解释器的微指令。 预测高速缓存存储器在多周期拍摄的地址处存储解释器呼叫预测和解释器输入地址。 当发生呼叫预测时,指令解释器的入口地址在紧接呼叫预测之后的处理周期被加载到程序计数器寄存器中,并且将返回地址推送到堆栈。 解释器的微指令从指令高速缓冲存储器中顺序取出。 当解释器完成时,预测高速缓冲存储器进行返回预测。 返回地址在返回预测之后的处理周期上从堆栈传送到程序计数器寄存器,并恢复正常的程序流程。 预测高速缓存存储器还存储分支指令预测和分支目标地址。
    • 38. 发明申请
    • APPARATUSES, METHODS AND SYSTEMS FOR AN INFORMATION COMPARATOR INTERFACE
    • 信息比较器接口的设备,方法和系统
    • US20100293479A1
    • 2010-11-18
    • US12443024
    • 2007-09-26
    • Armand RoussoSteven Schwartz
    • Armand RoussoSteven Schwartz
    • G06F3/048G06F17/30
    • G06Q30/02
    • A system for engaging in the comparison of information and/or advertising that is attractive, easy to navigate and straightforward The comparator interface allows users to compare and/or navigate through related and/or competing information and/or advertisements side-by-side In one embodiment, the information comparator interface displays several ads for a user to compare, in such an embodiment a single user selection will generate a side-by-side companson and result in several ad placements simultaneously As such, the information comparator interface may be employed by search engines, product companson engines, advertising, research and other venues The information comparator may act both as an application and as a flexible application program interface (API) that includes advances such as multi-pane viewing, multi-pane information placement, multi-pane click-thrus, comparative information navigations, and/or the like In one embodiment a single selection (e g, click) will present a user with a plurality of related information items (e g, ads)
    • 用于参与比较有吸引力,易于导航和简单的信息和/或广告的系统比较器接口允许用户在并排的方面比较和/或浏览相关和/或竞争的信息和/或广告In 在一个实施例中,信息比较器接口显示用于用户比较的几个广告,在这样的实施例中,单个用户选择将生成并排Companson并且同时导致多个广告布置。因此,可以使用信息比较器接口 搜索引擎,产品简介引擎,广告,研究和其他场所信息比较器可以作为应用程序和作为灵活的应用程序接口(API),包括多窗格查看,多窗格信息放置,多 在一个实施例中,单个选择(例如,点击)将呈现一个我们 具有多个相关信息项(例如,广告)