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31. 发明申请

US20160276010A1 NONVOLATILE MEMORY 有权
标题翻译：非易失性存储器
公开(公告)号：US20160276010A1
公开(公告)日：2016-09-22
申请号：US15067967
申请日：2016-03-11
申请人： Kabushiki Kaisha Toshiba
发明人： Satoshi TAKAYA , Hiroki NOGUCHI , Shinobu FUJITA
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/161 , G11C11/1659 , G11C11/1677 , G11C27/024 , G11C29/021 , G11C29/028
摘要： According to one embodiment, a nonvolatile memory includes a memory cell, a write circuit generating a write current to change the memory cell from a first resistance value to a second resistance value, a first current generating circuit generating a first current based on the write current flowing through the memory cell, a second current generating circuit generating a second current based on the write current flowing through the memory cell, a hold circuit holding a first value generated based on the second current when the memory cell stores the first resistance value, a comparator comparing the first value with a second value generated based on a change of the first current while the memory cell changes from the first resistance value to the second resistance value, and a write current control circuit cutting off the write current based on a result of comparison of the comparator.
摘要翻译：根据一个实施例，非易失性存储器包括存储单元，产生写入电流以将存储单元从第一电阻值改变为第二电阻值的写入电路;基于写入电流产生第一电流的第一电流产生电路流过所述存储单元的第二电流产生电路，基于流过所述存储单元的写入电流产生第二电流的保持电路，当所述存储单元存储所述第一电阻值时，保持电路基于所述第二电流产生的第一值; 将所述第一值与基于所述第一电流的变化而生成的第二值进行比较，同时所述存储单元从所述第一电阻值改变为所述第二电阻值，以及写入电流控制电路基于所述第一电流的结果切断所述写入电流比较比较。

32. 发明申请

US20160188429A1 MEMORY CONTROL CIRCUIT, CACHE MEMORY AND MEMORY CONTROL METHOD 审中-公开
标题翻译：存储器控制电路，高速缓存存储器和存储器控制方法
公开(公告)号：US20160188429A1
公开(公告)日：2016-06-30
申请号：US15059702
申请日：2016-03-03
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Hiroki NOGUCHI , Shinobu FUJITA , Keiko ABE
IPC分类号： G06F11/20 , G11C29/52 , G06F11/10
CPC分类号： G06F11/2069 , G06F11/1004 , G06F11/1064 , G06F11/1068 , G06F12/0802 , G06F12/16 , G11C11/1673 , G11C11/1675 , G11C11/1677 , G11C29/52 , G11C2029/0411
摘要： A memory control circuit has an error determination circuitry to determine whether an error-bit number is larger than a predetermined threshold value set based on a maximum number of error bits correctable by the error correction circuitry, when it is detected by the error detector that an error is contained in data read for verification of data written to the first memory or in data read from the first memory, and an access controller to control access to a second memory having an access priority lower than the first memory when it is determined that the error-bit number is larger than the threshold value, and to control access to the first memory without accessing the second memory when it is determined that the error-bit number is equal to or less than the threshold value.
摘要翻译：存储器控制电路具有错误确定电路，用于根据由误差校正电路校正的最大错误位数来确定错误位数是否大于设定的预定阈值，当错误检测电路被错误检测器检测到时，用于对写入第一存储器的数据或从第一存储器读取的数据进行验证的数据读取中包含错误;以及访问控制器，当确定存取控制器的访问优先级低于第一存储器时，控制对第二存储器的访问错误位数大于阈值，并且当确定错误位数等于或小于阈值时，控制对第一存储器的访问而不访问第二存储器。

33. 发明申请

US20130322161A1 MAGNETIC RANDOM ACCESS MEMORY 有权
标题翻译：磁性随机存取存储器
公开(公告)号：US20130322161A1
公开(公告)日：2013-12-05
申请号：US13772815
申请日：2013-02-21
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Hiroki NOGUCHI , Keiko ABE , Kazutaka IKEGAMI , Shinobu FUJITA
IPC分类号： G11C11/16
CPC分类号： G11C11/1673 , G11C11/1659 , G11C11/1675
摘要： According to one embodiment, a magnetic random access memory includes a write circuit to write complementary data to first and second magnetoresistive elements, and a read circuit to read the complementary data from the first and second magnetoresistive elements. The control circuit is configured to change the first and second bit lines to a floating state after setting the first and second bit lines to a first potential, and change a potential of the first bit line in the floating state to a first value in accordance with a resistance value of the first magnetoresistive element and a potential of the second bit line in the floating state to a second value in accordance with a resistance value of the second magnetoresistive element by setting the common source line to a second potential higher than the first potential.
摘要翻译：根据一个实施例，磁性随机存取存储器包括用于向第一和第二磁阻元件写入互补数据的写入电路，以及读取电路以从第一和第二磁阻元件读取互补数据。控制电路被配置为在将第一和第二位线设置为第一电位之后将第一和第二位线改变为浮置状态，并且将浮动状态下的第一位线的电位根据根据第二磁阻元件的电阻值将第一磁阻元件的电阻值和浮置状态下的第二位线的电位设置为第二值，将第二磁阻元件的电阻值设定为比第一电位高的第二电位。

34. 发明申请

US20130246818A1 CACHE DEVICE, CACHE SYSTEM AND CONTROL METHOD 有权
标题翻译：缓存设备，缓存系统和控制方法
公开(公告)号：US20130246818A1
公开(公告)日：2013-09-19
申请号：US13772518
申请日：2013-02-21
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kumiko NOMURA , Shinobu FUJITA , Keiko ABE , Kazutaka IKEGAMI , Hiroki NOGUCHI
IPC分类号： G06F1/32
CPC分类号： G06F1/3275 , G06F1/32 , G06F1/3225 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： According to an embodiment, a cache device includes a cache memory, an access controller, and a power controller. The cache memory includes a plurality of memory areas associated with a plurality of ways, respectively. The access controller controls access to the memory areas. The power controller controls power supplied to each of the memory areas individually such that power supplied to a memory area that has not been accessed for a predetermined time is standby power that is lower than operating power that enables the memory area to operate. The power controller controls power supplied to a memory area such that standby power for a memory area that is highly likely to be accessed has a value closer to the operating power than a value of standby power for a memory area that is less likely to be accessed.
摘要翻译：根据实施例，高速缓存设备包括高速缓冲存储器，访问控制器和功率控制器。高速缓冲存储器分别包括与多个方式相关联的多个存储区域。访问控制器控制对存储区域的访问。功率控制器单独地控制提供给每个存储器区域的功率，使得提供给在预定时间内未被访问的存储区域的功率是低于使得存储区域能够操作的操作功率的待机功率。功率控制器控制提供给存储区域的功率，使得对于很可能被访问的存储区域的待机功率具有比不太可能被访问的存储区域的待机功率值更接近操作功率的值。

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