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31. 发明授权

US6094380A Memory device with a data output buffer and the control method thereof 有权
标题翻译：具有数据输出缓冲器的存储器件及其控制方法
公开(公告)号：US6094380A
公开(公告)日：2000-07-25
申请号：US221344
申请日：1998-12-28
申请人： Jung Pill Kim
发明人： Jung Pill Kim
IPC分类号： G11C11/417 , G11C7/00 , G11C7/10 , G11C11/407 , G11C11/409 , G11C15/00
CPC分类号： G11C7/1057 , G11C7/1039 , G11C7/1051 , G11C7/106
摘要： A memory device with a data output buffer outputs the read data from the memory cell array without error and provides sufficent time in outputting the data. A memory device with a data output buffer means comprises a clock input buffer means for receiving an external clock and outputting an internal clock; and a delay means for delaying a specified time the internal clock outputted from the clock input buffer means; wherein the operation of the data output buffer means is controlled by the delayed internal clock outputted from the delay means.
摘要翻译：具有数据输出缓冲器的存储器件输出来自存储单元阵列的读取数据而没有错误，并且在输出数据时提供足够的时间。具有数据输出缓冲器装置的存储器件包括用于接收外部时钟并输出内部时钟的时钟输入缓冲器装置; 以及延迟装置，用于将指定时间延迟从时钟输入缓冲器装置输出的内部时钟; 其中数据输出缓冲器装置的操作由延迟装置输出的延迟的内部时钟控制。

32. 发明授权

US6041009A Apparatus for stabilizing an antifuse used for a memory device 有权
标题翻译：用于稳定用于存储器件的反熔丝的装置
公开(公告)号：US6041009A
公开(公告)日：2000-03-21
申请号：US206318
申请日：1998-12-07
申请人： Jung Pill Kim , In Chul Jung
发明人： Jung Pill Kim , In Chul Jung
IPC分类号： G11C16/04 , G11C17/14 , G11C29/04 , H01L21/82 , H01L27/085 , G11C7/00
CPC分类号： G11C17/14
摘要： An antifuse stabilizing apparatus for a memory device stabilizes a programming process of an antifuse. A serial antifuse block has a plurality of antifuses being interconnected in series, and is programmed by applying a voltage being higher than an appropriate applying voltage of each antifuse. An antifuse programming block applies a program voltage being higher than the appropriate applying voltage to both ends of each antifuse in order to program the antifuses. A high voltage portion and a low voltage portion check a coupling state of the antifuses of the serial antifuse block. The applying voltage higher than the appropriate applying voltage is a voltage to be applied to both ends of each antifuse by the antifuse programming block. As a result, all circuits of using an antifuse whose appropriate applying voltage is lower than a power-supply voltage of the peripheral circuit can use the antifuse stably without using an additional circuit.
摘要翻译：用于存储器件的反熔丝稳定装置稳定了反熔丝的编程过程。串联反熔丝块具有串联互连的多个反熔丝，并且通过施加高于每个反熔丝的适当施加电压的电压来编程。反熔丝编程块对每个反熔丝的两端施加高于适当施加电压的编程电压，以便对反熔丝进行编程。高电压部分和低电压部分检查串联反熔丝块的反熔丝的耦合状态。高于适当施加电压的施加电压是通过反熔丝编程块施加到每个反熔丝两端的电压。结果，使用适当施加电压低于外围电路的电源电压的反熔丝的所有电路可以稳定地使用反熔丝而不使用附加电路。

33. 发明授权

US5963077A Auto mode selector 失效
标题翻译：自动模式选择器
公开(公告)号：US5963077A
公开(公告)日：1999-10-05
申请号：US864471
申请日：1997-05-28
申请人： Jung Pill Kim
发明人： Jung Pill Kim
IPC分类号： G11C11/407 , G11C5/14 , G11C7/10 , G11C11/401 , G11C11/409 , H03K17/00 , H03K17/22 , H03K17/62
CPC分类号： H03K17/223 , G11C7/1045 , G11C7/1051 , G11C7/1078 , H03K2217/0036
摘要： An auto mode selector for a semiconductor memory device having a reference voltage selection switching circuit connected between a reference voltage pin and an internal reference voltage terminal, for selecting one of CTT and LVTTL in response to a reference voltage selection signal. The auto mode selector further includes an input leakage current controller for allowing current to flow through a resistor between a supply voltage source and the reference voltage pin only for a predetermined time period in response to an input leakage current control signal from an input leakage current control signal generator. According to the present invention, the amount of input leakage current and standby current can be reduced.
摘要翻译：一种用于半导体存储器件的自动模式选择器，具有连接在参考电压引脚和内部参考电压端子之间的参考电压选择开关电路，用于响应于参考电压选择信号选择CTT和LVTTL之一。自动模式选择器还包括输入漏电流控制器，用于响应于来自输入漏电流控制的输入泄漏电流控制信号，允许电流在电源电压源和参考电压引脚之间流过预定时间段内的电阻器信号发生器。根据本发明，可以减少输入漏电流和待机电流的量。

34. 发明授权

US5818790A Method for driving word lines in semiconductor memory device 失效
标题翻译：用于在半导体存储器件中驱动字线的方法
公开(公告)号：US5818790A
公开(公告)日：1998-10-06
申请号：US777224
申请日：1996-12-27
申请人： Jung Pill Kim , Kee Woo Park
发明人： Jung Pill Kim , Kee Woo Park
IPC分类号： G11C11/407 , G11C8/08 , G11C8/10 , H01L21/8242 , H01L27/108 , G11C8/00
CPC分类号： G11C8/10 , G11C8/08
摘要： A method for driving word lines in a semiconductor memory device. A main row decoder generates a word line enable signal in s response to one part of address signal bits and a sub row decoder generates a word line boosting signal in response to the other part of the address signal bits. A bootstrap transistor transfers the word line enable signal from the main row decoder to a bootstrap node in response to a specific voltage. A high level voltage transfer transistor transfers the word line boosting signal from the sub row decoder to a corresponding one of the word lines in response to a voltage at the bootstrap node. After the word line enable signal from the main row decoder makes a low to high transition in level, the word line boosting signal from the sub row decoder is changed from a ground voltage level to a high voltage level to drive the corresponding word line. Then, the specific voltage is changed from the present level to the lower level. According to the present invention, the word line driving method can prevent a selected word line from floating due to OFF current resulting from a low level voltage at the bootstrap node when a row address strobe signal has a long duration. Furthermore, the word line driving method has the effect of enhancing the bootstrapping efficiency.
摘要翻译：一种用于在半导体存储器件中驱动字线的方法。主行解码器响应于一部分地址信号位产生字线使能信号，并且子行解码器响应于地址信号位的另一部分产生字线升压信号。自举晶体管响应于特定电压将字线使能信号从主行解码器传送到引导节点。响应于引导节点处的电压，高电平电压传输晶体管将字线升压信号从子行解码器传送到对应的字线。在来自主行解码器的字线使能信号从低电平到高电平转换之后，来自子行解码器的字线升压信号从接地电压电平变为高电平来驱动相应的字线。然后，具体电压从当前电平变为较低电平。根据本发明，当行地址选通信号具有长持续时间时，字线驱动方法可以防止所选择的字线由于在引导节点处的低电平电压导致的OFF电流而浮置。此外，字线驱动方法具有提高自举效率的效果。

35. 发明授权

US09147457B2 Reference cell repair scheme 有权
标题翻译：参考细胞修复方案
公开(公告)号：US09147457B2
公开(公告)日：2015-09-29
申请号：US13613038
申请日：2012-09-13
申请人： Jung Pill Kim , Taehyun Kim , Sungryul Kim
发明人： Jung Pill Kim , Taehyun Kim , Sungryul Kim
IPC分类号： G11C11/00 , G11C11/16 , G11C29/00
CPC分类号： G11C11/16 , G11C11/165 , G11C11/1673 , G11C29/787 , G11C29/832
摘要： In a magnetic random access memory (MRAM), numerous arrays of reference bit cells are coupled together by coupling their respective bit lines to a merged reference node. Pass gate circuitry coupled between the respective reference bit lines and the merged reference node is configured for selectively coupling or decoupling one or more of the reference bit lines to and from the merged reference node. The pass gate circuitry is controllable by programming one-time programmable devices coupled to the pass gate circuitry. The one-time programmable devices can be programmed to decouple flawed arrays of reference bit cells from the merged reference node or to select between redundant arrays of reference bit cells for coupling to the reference node.
摘要翻译：在磁随机存取存储器（MRAM）中，参考位单元的多个阵列通过将它们各自的位线耦合到合并的参考节点而耦合在一起。耦合在相应的参考位线和合并的参考节点之间的通过门电路被配置用于选择性地将一个或多个参考位线耦合或去耦合到合并的参考节点。传递门电路可通过编程耦合到通路电路的一次可编程器件来控制。一次性可编程器件可以被编程为将参考位单元的有缺陷的阵列与合并的参考节点去耦，或者在用于耦合到参考节点的参考位单元的冗余阵列之间进行选择。

36. 发明申请

US20140071738A1 REFERENCE CELL REPAIR SCHEME 有权
标题翻译：参考细胞修复方案
公开(公告)号：US20140071738A1
公开(公告)日：2014-03-13
申请号：US13613038
申请日：2012-09-13
申请人： Jung Pill Kim , Taehyun Kim , Sungryul Kim
发明人： Jung Pill Kim , Taehyun Kim , Sungryul Kim
IPC分类号： G11C11/16
CPC分类号： G11C11/16 , G11C11/165 , G11C11/1673 , G11C29/787 , G11C29/832
摘要： In a magnetic random access memory (MRAM), numerous arrays of reference bit cells are coupled together by coupling their respective bit lines to a merged reference node. Pass gate circuitry coupled between the respective reference bit lines and the merged reference node is configured for selectively coupling or decoupling one or more of the reference bit lines to and from the merged reference node. The pass gate circuitry is controllable by programming one-time programmable devices coupled to the pass gate circuitry. The one-time programmable devices can be programmed to decouple flawed arrays of reference bit cells from the merged reference node or to select between redundant arrays of reference bit cells for coupling to the reference node.
摘要翻译：在磁随机存取存储器（MRAM）中，参考位单元的多个阵列通过将它们各自的位线耦合到合并的参考节点而耦合在一起。耦合在相应的参考位线和合并的参考节点之间的通过门电路被配置用于选择性地将一个或多个参考位线耦合或去耦合到合并的参考节点。传递门电路可通过编程耦合到通路电路的一次可编程器件来控制。一次性可编程器件可以被编程为将参考位单元的有缺陷的阵列与合并的参考节点去耦，或者在用于耦合到参考节点的参考位单元的冗余阵列之间进行选择。

37. 发明申请

US20140050019A1 MULTI-LEVEL MEMORY CELL USING MULTIPLE MAGNETIC TUNNEL JUNCTIONS WITH VARYING MGO THICKNESS 有权
标题翻译：使用多个磁性隧道结的多级存储器单元与不同的MGO厚度
公开(公告)号：US20140050019A1
公开(公告)日：2014-02-20
申请号：US13589315
申请日：2012-08-20
申请人： Kangho Lee , Taehyun Kim , Jung Pill Kim , Seung H. Kang
发明人： Kangho Lee , Taehyun Kim , Jung Pill Kim , Seung H. Kang
IPC分类号： G11C11/16 , H01L21/8239 , B05C11/00 , H01L43/12
CPC分类号： G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C11/5607 , H01L21/00
摘要： A Multi-Level Memory Cell (MLC) using multiple Magnetic Tunnel Junction (MTJ) structures having one or more layers with varying thickness is disclosed. The multiple MTJ structures, which are vertically stacked and arranged in series, may have substantially identical area dimensions to minimize fabrication costs because one mask can be used to pattern the multiple MTJ structures. Further, varying the thicknesses associated with the one or more layers may provide the multiple MTJ structures with different switching current densities and thereby increase memory density and improve read and write operations. In one embodiment, the layers with the varying thicknesses may include tunnel barriers or magnesium oxide layers associated with the multiple MTJ structures and/or free layers associated with the multiple MTJ structures.
摘要翻译：公开了使用具有一层或多层具有变化厚度的多个磁隧道结（MTJ）结构的多层存储单元（MLC）。垂直堆叠和串联布置的多个MTJ结构可以具有基本上相同的面积尺寸以最小化制造成本，因为可以使用一个掩模来对多个MTJ结构进行图案化。此外，改变与一个或多个层相关联的厚度可以为多个MTJ结构提供不同的开关电流密度，从而增加存储器密度并改善读取和写入操作。在一个实施例中，具有变化厚度的层可以包括与多个MTJ结构相关联的隧道势垒或氧化镁层，和/或与多个MTJ结构相关联的自由层。

38. 发明授权

US08625338B2 Asymmetric write scheme for magnetic bit cell elements 有权
标题翻译：磁位元件的非对称写入方案
公开(公告)号：US08625338B2
公开(公告)日：2014-01-07
申请号：US12755978
申请日：2010-04-07
申请人： Xiaochun Zhu , Hari M. Rao , Jung Pill Kim , Seung H. Kang
发明人： Xiaochun Zhu , Hari M. Rao , Jung Pill Kim , Seung H. Kang
IPC分类号： G11C11/14
CPC分类号： G11C11/1675 , G11C11/16 , G11C11/1659 , G11C11/1693
摘要： Asymmetric switching is defined for magnetic bit cell elements. A magnetic bit cell for memory and other devices includes a transistor coupled to an MTJ structure. A bit line is coupled at one terminal of the bit cell to the MTJ structure. At another terminal of the bit cell, a source line is coupled to the source/drain terminal of the transistor. The bit line is driven by a bit line driver that provides a first voltage. The source line is driven by a source line driver that provides a second voltage. The second voltage is larger than the first voltage. The switching characteristics of the bit cell and MTJ structure are improved and made more reliable by one or a combination of applying the higher second voltage to the source line and/or reducing the overall parasitic resistance in the magnetic bit cell element.
摘要翻译：磁比特元件定义了非对称开关。用于存储器和其它器件的磁位单元包括耦合到MTJ结构的晶体管。位线在位单元的一个端子耦合到MTJ结构。在位单元的另一个端子处，源极线耦合到晶体管的源极/漏极端子。位线由提供第一电压的位线驱动器驱动。源极线由提供第二电压的源极线驱动器驱动。第二电压大于第一电压。通过将较高的第二电压施加到源极线和/或降低磁头单元元件中的整体寄生电阻的一个或组合来提高位单元和MTJ结构的开关特性并使其变得更可靠。

39. 发明授权

US08611132B2 Self-body biasing sensing circuit for resistance-based memories 有权
标题翻译：用于基于电阻的存储器的自身偏置感测电路
公开(公告)号：US08611132B2
公开(公告)日：2013-12-17
申请号：US13346029
申请日：2012-01-09
申请人： Seong-Ook Jung , Jisu Kim , Youngdon Jung , Jung Pill Kim , Seung H. Kang
发明人： Seong-Ook Jung , Jisu Kim , Youngdon Jung , Jung Pill Kim , Seung H. Kang
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0069 , G11C7/06 , G11C7/14 , G11C11/16 , G11C13/004 , G11C16/26 , G11C16/28
摘要： A resistance based memory sensing circuit has reference current transistors feeding a reference node and a read current transistor feeding a sense node, each transistor has a substrate body at a regular substrate voltage during a stand-by mode and biased during a sensing mode at a body bias voltage lower than the regular substrate voltage. In one option the body bias voltage is determined by a reference voltage on the reference node. The substrate body at the regular substrate voltage causes the transistors to have a regular threshold voltage, and the substrate body at the body bias voltage causes the transistors to have a sense mode threshold voltage, lower than the regular threshold voltage.
摘要翻译：基于电阻的存储器感测电路具有馈送参考节点的参考电流晶体管和馈送感测节点的读取电流晶体管，每个晶体管在待机模式期间具有处于规则衬底电压的衬底主体，并且在身体的感测模式期间被偏置偏置电压低于正常基板电压。在一个选项中，体偏置电压由参考节点上的参考电压确定。处于规则衬底电压的衬底体使晶体管具有规则的阈值电压，并且在体偏置电压下的衬底体使晶体管具有低于常规阈值电压的感测模式阈值电压。

40. 发明申请

US20130293286A1 TUNABLE REFERENCE CIRCUIT 有权
标题翻译：可控参考电路
公开(公告)号：US20130293286A1
公开(公告)日：2013-11-07
申请号：US13464242
申请日：2012-05-04
申请人： Xia Li , Jung Pill Kim , Taehyun Kim
发明人： Xia Li , Jung Pill Kim , Taehyun Kim
IPC分类号： G05F3/02 , H01L21/34
CPC分类号： G11C7/062 , G11C11/16 , G11C11/1673 , G11C11/5642
摘要： A circuit includes a first reference pair that includes a first path and a second path. The first path includes a first magnetic tunnel junction (MTJ) element, and the second path includes a second MTJ element. The circuit further includes a second reference pair that includes a third path and a fourth path. The third path includes a third MTJ element, and the fourth path includes a fourth MTJ element. The first reference pair and the second reference pair are tied together in parallel. A reference resistance of the circuit is based on a resistance of each of the first, second, third, and fourth MTJ elements. The reference resistance of the circuit is adjustable by adjusting a resistance of one of the MTJ elements.
摘要翻译：电路包括包括第一路径和第二路径的第一参考对。第一路径包括第一磁隧道结（MTJ）元件，第二路径包括第二MTJ元件。电路还包括第二参考对，其包括第三路径和第四路径。第三路径包括第三MTJ元件，第四路径包括第四MTJ元件。第一个参考对和第二个参考对并联在一起。电路的参考电阻基于第一，第二，第三和第四MTJ元件中的每一个的电阻。通过调整MTJ元件之一的电阻可以调节电路的参考电阻。

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