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31. 发明授权

US08680527B2 Photomask and thin-film transistor fabricated using the photomask 有权
标题翻译：使用光掩模制造的光掩模和薄膜晶体管
公开(公告)号：US08680527B2
公开(公告)日：2014-03-25
申请号：US12978446
申请日：2010-12-24
申请人： Yeon-Ju Kim , Sung-Jae Moon , Yun-Jung Cho , Bum-Ki Baek , Kwang-Hoon Lee , Byoung-Sun Na , Sung-Hoon Yang , Yoon-Jang Kim , Eun Cho
发明人： Yeon-Ju Kim , Sung-Jae Moon , Yun-Jung Cho , Bum-Ki Baek , Kwang-Hoon Lee , Byoung-Sun Na , Sung-Hoon Yang , Yoon-Jang Kim , Eun Cho
IPC分类号： H01L29/417
CPC分类号： G03F1/38 , G03F1/00 , G03F1/14 , G03F1/36 , H01L29/41733
摘要： A photomask includes; a source electrode pattern including; a first electrode portion which extends in a first direction, a second electrode portion which extends in the first direction and is substantially parallel to the first electrode portion, and a third electrode portion which extends from a first end of the first electrode portion to a first end of the second electrode portion and is rounded with a first curvature, a drain electrode pattern which extends in the first direction and is disposed between the first electrode portion and the second electrode portion, wherein an end of the drain electrode pattern is rounded to correspond to the third electrode portion; and a channel region pattern which is disposed between the source electrode pattern and the drain electrode pattern, wherein a center location of the first curvature and a center location of the rounded portion of the end of the drain electrode pattern are the same.
摘要翻译：光掩模包括; 源电极图案，包括：沿第一方向延伸的第一电极部分，沿第一方向延伸并基本上平行于第一电极部分的第二电极部分，以及从第一电极部分的第一端延伸到第一电极部分的第三电极部分，并且以第一曲率圆形化，漏电极图案，其沿第一方向延伸并且设置在第一电极部分和第二电极部分之间，其中漏极电极图案的端部被圆化以对应到所述第三电极部分; 以及设置在源极电极图案和漏极电极图案之间的沟道区域图案，其中第一曲率的中心位置和漏极电极图案的端部的圆形部分的中心位置相同。

32. 发明申请

US20120286274A1 DISPLAY SUBSTRATE INCLUDING AN AUXILIARY ELECTRODE 有权
标题翻译：显示基底包括辅助电极
公开(公告)号：US20120286274A1
公开(公告)日：2012-11-15
申请号：US13422686
申请日：2012-03-16
申请人： Min-Wook PARK , Jong-In Kim , Jun-Ho Song , Bum-Ki Baek , Young-Soo Yoon
发明人： Min-Wook PARK , Jong-In Kim , Jun-Ho Song , Bum-Ki Baek , Young-Soo Yoon
IPC分类号： H01L33/08
CPC分类号： H01L27/124 , G02F1/1362 , H01L27/1255
摘要： A display substrate includes a data line, a main gate line, and a first sub-pixel electrode formed on a base substrate. The display substrate further includes a first switching element connected to the data line. The display substrate further includes a second switching element connected to the data line, the main gate line, and a second sub-pixel electrode spaced apart from the first sub-pixel electrode. The display substrate further includes a third switching element connected to the data line and a secondary gate line adjacent to the main gate line. The display substrate further includes a shielding line spaced apart from the first and second sub-pixel electrodes, the shielding line overlapping the data line and receiving a reference voltage. The display substrate further includes an auxiliary electrode extending from the shielding line and overlapping an end electrode connected to the third switching element.
摘要翻译：显示基板包括形成在基底基板上的数据线，主栅线和第一子像素电极。显示基板还包括连接到数据线的第一开关元件。显示基板还包括连接到数据线，主栅极线和与第一子像素电极间隔开的第二子像素电极的第二开关元件。显示基板还包括连接到数据线的第三开关元件和与主栅极线相邻的次级栅极线。显示基板还包括与第一和第二子像素电极间隔开的屏蔽线，屏蔽线与数据线重叠并接收参考电压。显示基板还包括从屏蔽线延伸并与连接到第三开关元件的端电极重叠的辅助电极。

33. 发明申请

US20090283769A1 METHOD FOR MANUFACTURING A THIN FILM TRANSISTOR ARRAY PANEL FOR A LIQUID CRYSTAL DISPLAY AND A PHOTOLITHOGRAPHY METHOD FOR FABRICATING THIN FILMS 有权
标题翻译：制造液晶显示器的薄膜晶体管阵列的方法和用于制造薄膜的光刻方法
公开(公告)号：US20090283769A1
公开(公告)日：2009-11-19
申请号：US12467967
申请日：2009-05-18
申请人： Woon-Yong PARK , Bum-Ki Baek
发明人： Woon-Yong PARK , Bum-Ki Baek
IPC分类号： H01L33/00 , H01L29/786
CPC分类号： H01L27/1288 , G02F1/13458 , G02F1/136204 , G02F1/136227 , G02F2001/136236 , H01L27/1214
摘要： A gate wire including a plurality of gate lines and gate electrodes in the display area, and gate pads in the peripheral area is formed on a substrate having a display area and a peripheral area. A gate insulating layer, a semiconductor layer, an ohmic contact layer and a conductor layer are sequentially deposited, and the conductor layer and the ohmic contact are patterned to form a data wire including a plurality of data lines, a source electrode and a drain electrode of the display area and data pads of the peripheral area, and an ohmic contact layer pattern thereunder. A passivation layer is deposited and a positive photoresist layer is coated thereon. The photoresist layer is exposed to light through one or more masks having different transmittance between the display area and the peripheral area. The photoresist layer is developed to form a photoresist pattern having the thickness that varies depending on the position. At this time, a thin portion and a thick portion of the photoresist pattern are provided for the display area, and a thick portion and a zero thickness portion for the peripheral area. In the peripheral area, the portions of the passivation layer, the semiconductor layer and the gate insulating layer on the gate pads, and the portions of the passivation layer on the data pads, under the zero thickness portion, are removed. In the display area, the thin portion of the photoresist pattern, and the portions of the passivation layer and the semiconductor layer thereunder are removed but the portions of the passivation layer under the thick portions of the photoresist pattern is not removed. Then, a plurality of pixel electrodes, redundant gate pads and redundant data pads are formed.
摘要翻译：在具有显示区域和周边区域的基板上形成包括显示区域中的多个栅极线和栅电极的栅极线以及周边区域中的栅极焊盘。依次沉积栅极绝缘层，半导体层，欧姆接触层和导体层，并且对导体层和欧姆接触进行图案化以形成包括多条数据线，源电极和漏电极的数据线的周边区域的显示区域和数据焊盘以及其下的欧姆接触层图案。沉积钝化层，并在其上涂覆正性光致抗蚀剂层。光致抗蚀剂层通过在显示区域和周边区域之间具有不同透射率的一个或多个掩模曝光。光致抗蚀剂层被显影以形成具有根据位置而变化的厚度的光致抗蚀剂图案。此时，为显示区域设置有光致抗蚀剂图形的薄部分和厚部分，并且为周边区域设置厚部分和零厚度部分。在外围区域中，除去栅极焊盘上的钝化层，半导体层和栅极绝缘层的部分以及零厚度部分下的数据焊盘上的钝化层的部分。在显示区域中，去除了光致抗蚀剂图案的薄部分以及钝化层和其下面的半导体层的部分，但是未除去光致抗蚀剂图案的厚部下方的钝化层的部分。然后，形成多个像素电极，冗余栅极焊盘和冗余数据焊盘。

34. 发明授权

US07541225B2 Method of manufacturing a thin film transistor array panel that includes using chemical mechanical polishing of a conductive film to form a pixel electrode connected to a drain electrode 有权
标题翻译：制造薄膜晶体管阵列面板的方法，其包括使用导电膜的化学机械抛光来形成连接到漏电极的像素电极
公开(公告)号：US07541225B2
公开(公告)日：2009-06-02
申请号：US11332076
申请日：2006-01-13
申请人： Bum-Ki Baek , Hyuk-Jin Kim
发明人： Bum-Ki Baek , Hyuk-Jin Kim
IPC分类号： H01L21/84
CPC分类号： H01L27/1288 , H01L27/1214
摘要： A method of manufacturing a thin film transistor array panel is provided, the method including forming a thin film transistor having a gate electrode, a source electrode, and a drain electrode on a substrate, forming a passivation layer on the source electrode and the drain electrode, forming a photoresist film on the passivation layer, selectively etching the passivation layer using the photoresist film as a mask, forming a conductive film, and removing the photoresist film along with the conductive film disposed on the photoresist film using a CMP (chemical mechanical polishing) process to form a pixel electrode being connected to the drain electrode.
摘要翻译：提供一种制造薄膜晶体管阵列面板的方法，该方法包括在衬底上形成具有栅电极，源电极和漏电极的薄膜晶体管，在源电极和漏电极上形成钝化层在钝化层上形成光致抗蚀剂膜，使用光致抗蚀剂膜作为掩模选择性地蚀刻钝化层，形成导电膜，以及使用CMP（化学机械抛光）与设置在光致抗蚀剂膜上的导电膜一起除去光致抗蚀剂膜）处理以形成连接到漏电极的像素电极。

35. 发明申请

US20060194376A1 Thin film transistor array panel and manufacturing method thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20060194376A1
公开(公告)日：2006-08-31
申请号：US11332076
申请日：2006-01-13
申请人： Bum-Ki Baek , Hyuk-Jin Kim
发明人： Bum-Ki Baek , Hyuk-Jin Kim
IPC分类号： H01L21/84 , H01L31/113
CPC分类号： H01L27/1288 , H01L27/1214
摘要： A method of manufacturing a thin film transistor array panel is provided, the method including forming a thin film transistor having a gate electrode, a source electrode, and a drain electrode on a substrate, forming a passivation layer on the source electrode and the drain electrode, forming a photoresist film on the passivation layer, selectively etching the passivation layer using the photoresist film as a mask, forming a conductive film, and removing the photoresist film along with the conductive film disposed on the photoresist film using a CMP (chemical mechanical polishing) process to form a pixel electrode being connected to the drain electrode.
摘要翻译：提供一种制造薄膜晶体管阵列面板的方法，该方法包括在衬底上形成具有栅电极，源电极和漏电极的薄膜晶体管，在源电极和漏电极上形成钝化层在钝化层上形成光致抗蚀剂膜，使用光致抗蚀剂膜作为掩模选择性地蚀刻钝化层，形成导电膜，以及使用CMP（化学机械抛光）与设置在光致抗蚀剂膜上的导电膜一起除去光致抗蚀剂膜）处理以形成连接到漏电极的像素电极。

36. 发明授权

US07888677B2 Method for manufacturing a thin film transistor array panel for a liquid crystal display and a photolithography method for fabricating thin films 有权
标题翻译：液晶显示器用薄膜晶体管阵列面板的制造方法及薄膜制造用光刻方法
公开(公告)号：US07888677B2
公开(公告)日：2011-02-15
申请号：US12467967
申请日：2009-05-18
申请人： Woon-Yong Park , Bum-Ki Baek
发明人： Woon-Yong Park , Bum-Ki Baek
IPC分类号： H01L21/00
CPC分类号： H01L27/1288 , G02F1/13458 , G02F1/136204 , G02F1/136227 , G02F2001/136236 , H01L27/1214
摘要： A thin film transistor (TFT) array panel that includes a substrate, a gate wire including a gate pad, a gate insulating layer pattern, a semiconductor layer pattern, an ohmic contact layer pattern, a data wire including a data pad and a drain electrode, and a passivation layer pattern is presented. The passivation layer pattern is formed on the data wire and has contact holes exposing the gate pad, the data pad, and the drain electrode. The passivation layer pattern also has a planar shape that is similar that of the semiconductor layer pattern due to simultaneous etching except for the portions adjoining the drain electrode and the data pad, having a width greater than that of the data wire, and covering a boundary line of the data wire. A pixel electrode is electrically connected to the exposed portion of the drain electrode and contacts the gate insulating layer pattern.
摘要翻译：一种薄膜晶体管（TFT）阵列面板，其包括基板，包括栅极焊盘的栅极线，栅极绝缘层图案，半导体层图案，欧姆接触层图案，包括数据焊盘和漏极的数据线，并且呈现钝化层图案。钝化层图案形成在数据线上，并且具有暴露栅极焊盘，数据焊盘和漏电极的接触孔。钝化层图案还具有与除了与漏极电极和数据焊盘相邻的部分之外的同时蚀刻而与半导体层图案类似的平面形状，其宽度大于数据线的宽度，并且覆盖边界线数据线。像素电极电连接到漏电极的露出部分并接触栅极绝缘层图案。

37. 发明授权

US07537977B2 Method for manufacturing a thin film transistor array panel for a liquid crystal display and a photolithography method for fabricating thin films 有权
标题翻译：液晶显示器用薄膜晶体管阵列面板的制造方法及薄膜制造用光刻方法
公开(公告)号：US07537977B2
公开(公告)日：2009-05-26
申请号：US11716228
申请日：2007-03-09
申请人： Woon-Yong Park , Bum-Ki Baek
发明人： Woon-Yong Park , Bum-Ki Baek
IPC分类号： H01L21/00
CPC分类号： H01L27/1288 , G02F1/13458 , G02F1/136204 , G02F1/136227 , G02F2001/136236 , H01L27/1214
摘要： A thin film transistor (TFT) array panel that includes a substrate, a gate wire formed on the substrate, a gate insulating layer pattern formed on the gate wire, a semiconductor layer pattern formed on the gate insulating layer pattern, an ohmic contact layer pattern formed on the semiconductor layer pattern, a data wire formed on the ohmic contact layer pattern, a passivation layer pattern formed on the data wire, and a pixel electrode is presented. The data wire includes a data pad. The ohmic contact layer pattern includes a portion disposed under the data pad that is simultaneously etched as the data pad, and a contact hole in the passivation layer is etched simultaneously as a contact hole in the gate insulating layer.
摘要翻译：一种薄膜晶体管（TFT）阵列面板，其包括基板，形成在基板上的栅极线，形成在栅极线上的栅极绝缘层图案，形成在栅极绝缘层图案上的半导体层图案，欧姆接触层图案形成在半导体层图案上，形成在欧姆接触层图案上的数据线，形成在数据线上的钝化层图案和像素电极。数据线包括数据焊盘。欧姆接触层图案包括设置在数据焊盘下方的同时作为数据焊盘蚀刻的部分，并且钝化层中的接触孔同时被蚀刻作为栅极绝缘层中的接触孔。

38. 发明授权

US07440040B2 Liquid crystal display device with storage electrode extension 有权
标题翻译：液晶显示装置，带有电极延伸
公开(公告)号：US07440040B2
公开(公告)日：2008-10-21
申请号：US11460380
申请日：2006-07-27
申请人： Sang-Ki Kwak , Jung-Joon Park , Bum-Ki Baek , Kyung-Phil Lee
发明人： Sang-Ki Kwak , Jung-Joon Park , Bum-Ki Baek , Kyung-Phil Lee
IPC分类号： G02F1/1343
CPC分类号： G02F1/1393 , G02F1/134309 , G02F1/13439
摘要： A liquid crystal display (LCD) includes a gate line, a data line, and a pixel electrode including first and second sub-pixel electrodes to which different voltages are applied. A thin film transistor is coupled with the gate line and the data line to apply a voltage to the pixel electrode, and a storage electrode partially overlaps with the first and second sub-pixel electrodes. The first sub-pixel electrode is arranged on all but one side of the second sub-pixel electrode, portions of a first side of the storage electrode overlap with the boundaries of the first and second sub-pixel electrodes, portions of a second side of the storage electrode protrude and partially overlap with the second sub-pixel electrode, and the storage electrode comprises a storage electrode extension, which protrudes from the second side of the storage electrode across the first sub-pixel electrode and overlaps with the second sub-pixel electrode.
摘要翻译：液晶显示器（LCD）包括栅极线，数据线和包括施加不同电压的第一和第二子像素电极的像素电极。薄膜晶体管与栅极线和数据线耦合以向像素电极施加电压，并且存储电极与第一和第二子像素电极部分重叠。第一子像素电极配置在第二子像素电极的除了一侧之外，存储电极的第一侧的部分与第一和第二子像素电极的边界重叠，第二侧的部分存储电极突出并与第二子像素电极部分重叠，并且存储电极包括存储电极延伸部，其从存储电极的第二侧穿过第一子像素电极突出并与第二子像素重叠电极。

39. 发明授权

US07202502B2 Method for manufacturing a thin film transistor array panel for a liquid crystal display and a photolithography method for fabricating thin films 有权
标题翻译：液晶显示器用薄膜晶体管阵列面板的制造方法及薄膜制造用光刻方法
公开(公告)号：US07202502B2
公开(公告)日：2007-04-10
申请号：US11233038
申请日：2005-09-23
申请人： Woon-Yong Park , Bum-Ki Baek
发明人： Woon-Yong Park , Bum-Ki Baek
IPC分类号： H01L29/04
CPC分类号： H01L27/1288 , G02F1/13458 , G02F1/136204 , G02F1/136227 , G02F2001/136236 , H01L27/1214
摘要： A gate wire including a plurality of gate lines and gate electrodes in the display area, and gate pads in the peripheral area is formed on a substrate having a display area and a peripheral area. A gate insulating layer, a semiconductor layer, an ohmic contact layer and a conductor layer are sequentially deposited, and the conductor layer and the ohmic contact are patterned to form a data wire including a plurality of data lines, a source electrode and a drain electrode of the display area and data pads of the peripheral area, and an ohmic contact layer pattern thereunder. A passivation layer is deposited and a positive photoresist layer is coated thereon. The photoresist layer is exposed to light through one or more masks having different transmittance between the display area and the peripheral area. The photoresist layer is developed to form a photoresist pattern having the thickness that varies depending on the position. At this time, a thin portion and a thick portion of the photoresist pattern are provided for the display area, and a thick portion and a zero thickness portion for the peripheral area. In the peripheral area, the portions of the passivation layer, the semiconductor layer and the gate insulating layer on the gate pads, and the portions of the passivation layer on the data pads, under the zero thickness portion, are removed. In the display area, the thin portion of the photoresist pattern, and the portions of the passivation layer and the semiconductor layer thereunder are removed but the portions of the passivation layer under the thick portions of the photoresist pattern is not removed. Then, a plurality of pixel electrodes, redundant gate pads and redundant data pads are formed.
摘要翻译：在具有显示区域和周边区域的基板上形成包括显示区域中的多个栅极线和栅电极的栅极线以及周边区域中的栅极焊盘。依次沉积栅极绝缘层，半导体层，欧姆接触层和导体层，并且对导体层和欧姆接触进行图案化以形成包括多条数据线，源电极和漏电极的数据线的周边区域的显示区域和数据焊盘以及其下的欧姆接触层图案。沉积钝化层，并在其上涂覆正性光致抗蚀剂层。光致抗蚀剂层通过在显示区域和周边区域之间具有不同透射率的一个或多个掩模曝光。光致抗蚀剂层被显影以形成具有根据位置而变化的厚度的光致抗蚀剂图案。此时，为显示区域设置有光致抗蚀剂图形的薄部分和厚部分，并且为周边区域设置厚部分和零厚度部分。在外围区域中，除去栅极焊盘上的钝化层，半导体层和栅极绝缘层的部分以及零厚度部分下的数据焊盘上的钝化层的部分。在显示区域中，去除了光致抗蚀剂图案的薄部分以及钝化层和其下面的半导体层的部分，但是未除去光致抗蚀剂图案的厚部下方的钝化层的部分。然后，形成多个像素电极，冗余栅极焊盘和冗余数据焊盘。

40. 发明授权

US06256077B1 Thin film transistor array panel for a liquid crystal display and a method for manufacturing the same using four photolithography steps 有权
标题翻译：用于液晶显示器的薄膜晶体管阵列面板及其制造方法使用四个光刻步骤
公开(公告)号：US06256077B1
公开(公告)日：2001-07-03
申请号：US09425050
申请日：1999-10-22
申请人： Bum-Ki Baek
发明人： Bum-Ki Baek
IPC分类号： G02F11343
CPC分类号： H01L29/66765 , G02F1/13458 , G02F1/136227 , G02F1/136286
摘要： A gate wire including a gate line, a gate electrode and a gate pad is formed in the horizontal direction by a dry or wet etching method using a first mask. A gate insulating layer, an amorphous silicon layer, a doped amorphous silicon layer, and a data conductor layer are sequentially deposited and patterned by using a second mask to form a data wire and an etch protection layer located on the gate wire on each side of the data line. Subsequently, the doped amorphous silicon layer, which is not covered by the data wire and the etch protection layer, is etched. Next, a passivation layer is deposited and patterned along with the gate insulating layer and the semiconductor layer by using a third mask to form contact holes and an opening respectively exposing the drain electrode, the data pad, the gate pad, and the etch protection layer. After this step, an ITO layer is deposited and patterned by using a fourth mask to form a pixel electrode, a redundant gate pad and a redundant data pad, which are respectively connected to the contact hole. Next, the protection layer, the amorphous silicon layer and the doped amorphous silicon layer under the opening are sequentially etched until the gate insulating layer is exposed through the opening, thereby dividing the amorphous silicon layer under the two neighboring data lines without using an additional mask. At this time, it is preferable that an etchant is used that has a high etching selectivity between the gate insulating layer and the amorphous layer.
摘要翻译：通过使用第一掩模的干式或湿式蚀刻方法，在水平方向上形成包括栅极线，栅极电极和栅极焊盘的栅极线。通过使用第二掩模来顺序地沉积栅极绝缘层，非晶硅层，掺杂非晶硅层和数据导体层并形成图案，以形成位于栅极线的每一侧的数据线和蚀刻保护层数据线。随后，蚀刻不被数据线和蚀刻保护层覆盖的掺杂非晶硅层。接下来，通过使用第三掩模将钝化层与栅极绝缘层和半导体层一起沉积并图案化以形成分别暴露漏电极，数据焊盘，栅极焊盘和蚀刻保护层的接触孔和开口。在该步骤之后，通过使用第四掩模来沉积和图案化ITO层以形成分别连接到接触孔的像素电极，冗余栅极焊盘和冗余数据焊盘。接下来，依次蚀刻开口下的保护层，非晶硅层和掺杂非晶硅层，直到栅极绝缘层通过开口露出，从而在不使用附加掩模的情况下将非晶硅层划分在两个相邻的数据线之下。此时，优选使用在栅绝缘层和非晶层之间具有高蚀刻选择性的蚀刻剂。

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