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31. 发明申请

US20090283437A1 ITEM DISPENSER WITH MULTI-SECTION WELLS 审中-公开
标题翻译：具有多部分壁的物品分配器
公开(公告)号：US20090283437A1
公开(公告)日：2009-11-19
申请号：US12120310
申请日：2008-05-14
申请人： Karen Angelucci , Juliet McQuillan , Brian D. Johnson , Michael L. Forehand , Dean Whitney , Peter K. Bates , Alan Mudd , Janice Jackson , David Trapani , Adele Gulfo , Kathy Monday
发明人： Karen Angelucci , Juliet McQuillan , Brian D. Johnson , Michael L. Forehand , Dean Whitney , Peter K. Bates , Alan Mudd , Janice Jackson , David Trapani , Adele Gulfo , Kathy Monday
IPC分类号： B65D83/04
CPC分类号： A61J7/04 , A61J1/03 , A61J1/035 , A61J7/0084 , B65D75/327 , B65D83/0463 , B65D2575/3245
摘要： A solid dosage form dispenser, and methods for its manufacture. The dispenser may include at least one well having a first section and a second section; at least one well support configured to support the well; and an enclosure element for enclosing the well and the support. The first section may be deeper than the second section; and the well may be configured to dispense one solid dosage form.
摘要翻译：固体剂型分配器及其制造方法。分配器可以包括具有第一部分和第二部分的至少一个孔; 至少一个井支撑构造成支撑井; 以及用于封闭井和支撑件的封闭元件。第一部分可能比第二部分更深; 并且该孔可以被配置成分配一个固体剂型。

32. 发明授权

US07535275B1 High-performance memory interface circuit architecture 有权
标题翻译：高性能存储器接口电路架构
公开(公告)号：US07535275B1
公开(公告)日：2009-05-19
申请号：US11789598
申请日：2007-04-24
申请人： Joseph Huang , Chiakang Sung , Philip Pan , Yan Chong , Andy L. Lee , Brian D. Johnson
发明人： Joseph Huang , Chiakang Sung , Philip Pan , Yan Chong , Andy L. Lee , Brian D. Johnson
IPC分类号： H03L7/00
CPC分类号： H03L7/0812 , G11C7/22 , G11C7/222 , H03L7/0805
摘要： A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.
摘要翻译：可编程存储器接口电路包括可编程DLL延迟链，相位偏移控制电路和可编程DQS延迟链。 DLL延迟链使用一组串行连接的延迟单元，可编程开关，相位检测器和数字计数器来产生粗略的相移控制设置。然后，粗略的相移控制设置用于预先计算静态残留相移控制设置或生成动态残留相移控制设置，其中一个由相位偏移控制电路选择以被加到或从粗略相移控制设置，以产生精细的相移控制设置。粗调和精细相移控制设置一致地产生相位延迟的DQS信号，其中心对准其相关联的DQ信号。

33. 发明授权

US07323903B1 Soft core control of dedicated memory interface hardware in a programmable logic device 有权
标题翻译：可编程逻辑器件中专用存储器接口硬件的软核控制
公开(公告)号：US07323903B1
公开(公告)日：2008-01-29
申请号：US11530708
申请日：2006-09-11
申请人： Andy L. Lee , Brian D. Johnson
发明人： Andy L. Lee , Brian D. Johnson
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , G11C7/10 , H03K19/17744
摘要： The present invention is directed to a soft core logic circuit implemented in a PLD that estimates an appropriate phase delay and applies the phase shift to a read strobe signal to align its rising and falling edges at the center of a data sampling window associated with a group of read data signals. The soft core logic circuit dynamically determines an appropriate phase-shift value for the read strobe signal and adjusts the phase-shift to accommodate the environmental changes. The soft core logic circuit also introduces into the PLD various intermediate signals from a phase-shift estimator and a programmable phase delay chain.
摘要翻译：本发明涉及在PLD中实现的软核逻辑电路，其估计适当的相位延迟并将相移施加到读选通信号，以将其上升沿和下降沿对准在与组相关联的数据采样窗口的中心的读数据信号。软核心逻辑电路动态地确定读选通信号的适当相移值，并调整相移以适应环境变化。软核逻辑电路还将来自相移估计器和可编程相位延迟链的各种中间信号引入到PLD中。

34. 发明授权

US07287189B1 I/O configuration and reconfiguration trigger through testing interface 有权
标题翻译：通过测试界面进行I / O配置和重新配置触发
公开(公告)号：US07287189B1
公开(公告)日：2007-10-23
申请号：US10603888
申请日：2003-06-25
申请人： Brian D. Johnson , Keith Duwel , Mario Guzman , Christopher F. Lane , Andy L. Lee
发明人： Brian D. Johnson , Keith Duwel , Mario Guzman , Christopher F. Lane , Andy L. Lee
IPC分类号： G06F11/00
CPC分类号： G01R31/318572
摘要： A reconfigurable device loads I/O configuration information from a diagnostic interface during testing. The device includes a configurable I/O connection for communicating values with other devices. A diagnostic interface communicates the value of the I/O connection to a tester. A diagnostic controller in the device has a first mode for communicating the value on the I/O connection to the tester via the diagnostic interface, and a second mode for receiving an I/O configuration attribute value for the I/O connection from the diagnostic interface thereby modifying the configuration of the I/O connection. The device also includes a configuration controller that retrieves device configuration information from a configuration device in response to a signal. The signal can originate from an external source or from the diagnostic controller in response to a configuration instruction received via the diagnostic interface. The diagnostic interface may be a JTAG interface.
摘要翻译：可重构设备在测试期间从诊断接口加载I / O配置信息。该设备包括用于与其他设备通信值的可配置I / O连接。诊断接口将I / O连接的值传送给测试仪。设备中的诊断控制器具有用于经由诊断接口将I / O连接上的值传送给测试器的第一模式，以及用于从诊断接收I / O连接的I / O配置属性值的第二模式接口，从而修改I / O连接的配置。该设备还包括配置控制器，其响应于信号从配置设备检索设备配置信息。响应于通过诊断接口接收的配置指令，该信号可以来自外部源或诊断控制器。诊断接口可以是JTAG接口。

35. 发明授权

US07176714B1 Multiple data rate memory interface architecture 有权
标题翻译：多数据速率存储器接口架构
公开(公告)号：US07176714B1
公开(公告)日：2007-02-13
申请号：US10857396
申请日：2004-05-27
申请人： Andy L. Lee , Brian D. Johnson
发明人： Andy L. Lee , Brian D. Johnson
IPC分类号： H03K19/173 , H03K19/177 , H03K19/094 , H03K19/0175 , G06F7/38
CPC分类号： G11C7/10 , H03K19/17744
摘要： The present invention provides a DQS bus for implementing high speed multiple-data-rate interface architectures in programmable logic devices. The DQS bus has a balanced tree structure between at least one data strobe circuit and a plurality of I/O register blocks.
摘要翻译：本发明提供了一种用于在可编程逻辑器件中实现高速多数据速率接口架构的DQS总线。 DQS总线在至少一个数据选通电路和多个I / O寄存器块之间具有平衡树结构。

36. 发明授权

US07123051B1 Soft core control of dedicated memory interface hardware in a programmable logic device 有权
标题翻译：可编程逻辑器件中专用存储器接口硬件的软核控制
公开(公告)号：US07123051B1
公开(公告)日：2006-10-17
申请号：US10873668
申请日：2004-06-21
申请人： Andy L. Lee , Brian D. Johnson
发明人： Andy L. Lee , Brian D. Johnson
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , G11C7/10 , H03K19/17744
摘要： The present invention is directed to a soft core logic circuit implemented in a PLD that estimates an appropriate phase delay and applies the phase shift to a read strobe signal to align its rising and falling edges at the center of a data sampling window associated with a group of read data signals. The soft core logic circuit dynamically determines an appropriate phase-shift value for the read strobe signal and adjusts the phase-shift to accommodate the environmental changes. The soft core logic circuit also introduces into the PLD various intermediate signals from a phase-shift estimator and a programmable phase delay chain.
摘要翻译：本发明涉及在PLD中实现的软核逻辑电路，其估计适当的相位延迟并将相移施加到读选通信号，以将其上升沿和下降沿对准在与组相关联的数据采样窗口的中心的读数据信号。软核心逻辑电路动态地确定读选通信号的适当相移值，并调整相移以适应环境变化。软核逻辑电路还将来自相移估计器和可编程相位延迟链的各种中间信号引入到PLD中。

37. 发明授权

US06661253B1 Passgate structures for use in low-voltage applications 有权
公开(公告)号：US06661253B1
公开(公告)日：2003-12-09
申请号：US09931475
申请日：2001-08-16
申请人： Andy L. Lee , Wanli Chang , Cameron McClintock , John E. Turner , Brian D. Johnson , Chiao Kai Hwang , Richard Yen-Hsiang Chang , Richard G. Cliff
发明人： Andy L. Lee , Wanli Chang , Cameron McClintock , John E. Turner , Brian D. Johnson , Chiao Kai Hwang , Richard Yen-Hsiang Chang , Richard G. Cliff
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K17/063 , H03K19/177 , H03K19/1778
摘要： Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE−Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.

38. 发明授权

US5941109A Method and apparatus for the registration of containers 失效
标题翻译：容器注册方法和装置
公开(公告)号：US5941109A
公开(公告)日：1999-08-24
申请号：US916213
申请日：1997-08-22
申请人： Brian D. Johnson , Frank L. O 'Brien , Randall E. Carr , Larry W. Ellis
发明人： Brian D. Johnson , Frank L. O 'Brien , Randall E. Carr , Larry W. Ellis
IPC分类号： B65D1/02 , B21D22/02 , B21D51/26
CPC分类号： B65D17/02 , B21D51/2646 , B65D2517/0056
摘要： A can body embossing apparatus has a first mandrel with a first tooling member adapted to receive thereon a can body and a second mandrel with a second tooling member reciprocally movable from a first position distal the first tooling member to a second position proximate the first tooling member. In the second position, the can body side wall is engaged between the first tooling member and the second tooling member. The first tooling member defines one or more recessed portions therein and the second tooling member defines one or more protuberances extending therefrom and adapted to correspond with the recessed portions. The first mandrel and second mandrel are in mechanical communication throughout the reciprocal movement of the second mandrel such that the first and second tooling members rotate continuously with respect to each other and maintain a substantially constant relative position with respect to each other. The continuous side wall of the can body is conveyed between the first and second tooling members to effect the embossing of the side wall resulting in the formation of decorative embossed features in the side wall.
摘要翻译：罐体压花装置具有第一心轴，其具有适于在其上容纳罐主体的第一工具构件和具有第二工具构件的第二心轴，第二工具构件可从第一工具构件远离第一位置往复移动到靠近第一工具构件的第二位置。在第二位置，罐主体侧壁接合在第一工具构件和第二工具构件之间。第一加工构件在其中限定一个或多个凹部，并且第二加工构件限定从其延伸并适于与凹部对应的一个或多个突起。第一心轴和第二心轴在第二心轴的往复运动中处于机械连通状态，使得第一和第二模具构件相对于彼此连续地旋转并保持相对于彼此基本上恒定的相对位置。罐体的连续侧壁在第一和第二加工构件之间传送以实现侧壁的压花，从而在侧壁中形成装饰性压花特征。

39. 发明申请

US20160189266A1 TECHNOLOGIES FOR RULE-GUIDED AUTONOMOUS GOAL ACHIEVEMENT 审中-公开
标题翻译：规范自主创新的技术
公开(公告)号：US20160189266A1
公开(公告)日：2016-06-30
申请号：US14583683
申请日：2014-12-27
申请人： Brian D. Johnson , Anthony C. Salvador
发明人： Brian D. Johnson , Anthony C. Salvador
IPC分类号： G06Q30/06
CPC分类号： G06Q30/0617 , G06Q30/0605
摘要： Technologies for autonomously determining conditions to achieve a goal include determining a goal to be achieved, determining a pool of available resources usable to achieve the goal, determining a set of rules to be satisfied to achieve the goal, updating the pool of available resources based on the determined set of rules, and determining the conditions required to achieve the goal utilizing resources from the updated pool of available resources that satisfies the set of rules. A set of final conditions may be determined to achieve a set of multiple goals. The goals, rules, and resources may be provided by a user, an agent of the resources, or otherwise determined or inferred by the disclosed system.
摘要翻译：用于自主确定实现目标的条件的技术包括确定要实现的目标，确定可用于实现目标的可用资源池，确定要满足的一组规则以实现目标，基于以下方式更新可用资源池确定的一套规则，并确定使用满足一组规则的可用资源的更新池资源实现目标所需的条件。可以确定一组最终条件以实现一组多个目标。目标，规则和资源可以由用户，资源的代理人提供，或者由公开的系统以其他方式确定或推断。

40. 外观设计

USD689921S1 Point of sale display 有权
公开(公告)号：USD689921S1
公开(公告)日：2013-09-17
申请号：US29429788
申请日：2012-08-16
申请人： James David Branck , Bernard Wesley Baker, Jr. , Brian D. Johnson , William J. Williams
设计人： James David Branck , Bernard Wesley Baker, Jr. , Brian D. Johnson , William J. Williams

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