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31. 发明授权

US06743641B2 Method of improving surface planarity prior to MRAM bit material deposition 有权
标题翻译：在MRAM钻头材料沉积之前提高表面平面度的方法
公开(公告)号：US06743641B2
公开(公告)日：2004-06-01
申请号：US10022721
申请日：2001-12-20
申请人： Donald L. Yates , Joel A. Drewes
发明人： Donald L. Yates , Joel A. Drewes
IPC分类号： H01L2100
CPC分类号： H01L27/222 , G11C11/15 , H01L21/7684
摘要： The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the flattened upper surface of the insulating layer and the first conductor and flattening an upper portion of the material layer while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.
摘要翻译：本发明提供了一种制造存储单元的一部分的方法，该方法包括提供一沟槽中的第一导体，其设置在绝缘层中并使绝缘层和第一导体的上表面平坦化，形成材料层在绝缘层和第一导体的平坦的上表面上方，并且使材料层的上部平坦化，同时在绝缘层和第一导体上完整地保留材料层的下部。

32. 发明授权

US06677631B1 MRAM memory elements and method for manufacture of MRAM memory elements 有权
标题翻译： MRAM存储器元件和用于制造MRAM存储元件的方法
公开(公告)号：US06677631B1
公开(公告)日：2004-01-13
申请号：US10228062
申请日：2002-08-27
申请人： Joel A. Drewes
发明人： Joel A. Drewes
IPC分类号： H01L31119
CPC分类号： H01L27/222 , H01L43/08
摘要： A magnetic memory element has reduced demagnetization coupling between a pinned layer and a free layer. The element includes a pinned ferromagnetic layer and a free ferromagnetic layer which are separated by a barrier layer. The pinned layer is pinned by an antiferromagnetic layer. An offset ferromagnetic layer is provided on a side of the antiferromagnetic layer opposite the pinned ferromagnetic layer to reduce demagnetization coupling between the free ferromagnetic layer and the pinned ferromagnetic layer.
摘要翻译：磁存储元件减少了被钉扎层和自由层之间的去磁耦合。元件包括被阻挡层分隔的钉扎铁磁层和自由铁磁层。被钉扎层被反铁磁层固定。偏转铁磁层设置在与被钉扎的铁磁层相对的反铁磁层的一侧上，以减少游离铁磁层与被钉扎的铁磁层之间的去磁耦合。

33. 发明授权

US06656371B2 Methods of forming magnetoresisitive devices 有权
标题翻译：形成磁感应装置的方法
公开(公告)号：US06656371B2
公开(公告)日：2003-12-02
申请号：US09966699
申请日：2001-09-27
申请人： Joel A. Drewes
发明人： Joel A. Drewes
IPC分类号： G11B5127
CPC分类号： H01L27/222 , B82Y10/00 , H01L43/12
摘要： The invention includes a method of forming a magnetoresistive device. A stack is formed. The stack comprises a first magnetic layer, a second magnetic layer, and a non-magnetic layer between the first and second magnetic layers. At least one of the first magnetic layer, second magnetic layer, and non-magnetic layer is etched with a primarily physical etch process in a reaction chamber to expose a portion of the etched layer. While the stack remains in the reaction chamber, a protective material is deposited over the exposed portion.
摘要翻译：本发明包括形成磁阻器件的方法。形成堆叠。该堆叠包括在第一和第二磁性层之间的第一磁性层，第二磁性层和非磁性层。通过在反应室中的主要物理蚀刻工艺来蚀刻第一磁性层，第二磁性层和非磁性层中的至少一个，以暴露蚀刻层的一部分。当堆栈保留在反应室中时，保护材料沉积在暴露部分上。

34. 发明授权

US07884405B2 Method for production of MRAM elements 有权
标题翻译：生产MRAM元件的方法
公开(公告)号：US07884405B2
公开(公告)日：2011-02-08
申请号：US12323998
申请日：2008-11-26
申请人： Joel A. Drewes
发明人： Joel A. Drewes
IPC分类号： H01L21/02
CPC分类号： H01L27/222 , G11C11/161 , H01L43/08 , H01L43/12
摘要： Magneto-resistive random access memory elements include a ferromagnetic layer having uniaxial anisotropy provided by elongate structures formed in the ferromagnetic film. The magnetic dipole aligns with the long axis of each structure. The structures can be formed in a variety of ways. For example, the ferromagnetic film can be applied to a seed layer having a textured surface. Alternatively, the ferromagnetic film can be stressed to generate the textured structure. Chemical mechanical polishing also can be used to generated the structures.
摘要翻译：磁阻随机存取存储元件包括由在铁磁膜中形成的细长结构提供的具有单轴各向异性的铁磁层。磁偶极子与每个结构的长轴对齐。可以以各种方式形成结构。例如，铁磁膜可以施加到具有纹理表面的种子层。或者，铁磁膜可以被应力以产生纹理结构。化学机械抛光也可用于生成结构。

35. 发明授权

US07855085B2 System and method for reducing shorting in memory cells 有权
标题翻译：用于减少存储器单元短路的系统和方法
公开(公告)号：US07855085B2
公开(公告)日：2010-12-21
申请号：US11535456
申请日：2006-09-26
申请人： Joel A. Drewes , James G. Deak
发明人： Joel A. Drewes , James G. Deak
IPC分类号： H01L21/70 , G11C11/15
CPC分类号： H01L27/222 , H01L43/08 , H01L43/12
摘要： An MRAM device includes an array of magnetic memory cells having an upper conductive layer and a lower conductive layer separated by a barrier layer. To reduce the likelihood of electrical shorting across the barrier layers of the memory cells, spacers can be formed around the upper conductive layer and, after the layers of the magnetic memory cells have been etched, the memory cells can be oxidized to transform any conductive particles that are deposited along the sidewalls of the memory cells as byproducts of the etching process into nonconductive particles. Alternatively, the lower conductive layer can be repeatedly subjected to partial oxidation and partial etching steps such that only nonconductive particles can be thrown up along the sidewalls of the memory cells as byproducts of the etching process.
摘要翻译： MRAM器件包括具有由阻挡层隔开的上导电层和下导电层的磁存储单元的阵列。为了减少跨越存储器单元的阻挡层的电短路的可能性，可以在上导电层周围形成间隔物，并且在已经蚀刻了磁存储单元的层之后，可以将存储单元氧化以转换任何导电颗粒沿着存储器单元的侧壁沉积作为蚀刻工艺的副产物而形成非导电颗粒。或者，下导电层可以重复进行部分氧化和部分蚀刻步骤，使得只有非导电颗粒可以作为蚀刻工艺的副产物沿着存储器单元的侧壁被抛出。

36. 发明申请

US20100167542A1 Methods of Titanium Deposition 有权
标题翻译：钛沉积方法
公开(公告)号：US20100167542A1
公开(公告)日：2010-07-01
申请号：US12720562
申请日：2010-03-09
申请人： Joel A. Drewes , Cem Basceri , Demetrius Sarigiannis
发明人： Joel A. Drewes , Cem Basceri , Demetrius Sarigiannis
IPC分类号： H01L21/3205
CPC分类号： H01L21/28562 , C23C16/06 , C23C16/45525 , H01L21/28518 , H01L21/76843 , Y10S438/913
摘要： Some embodiments include methods of titanium deposition in which a silicon-containing surface and an electrically insulative surface are both exposed to titanium-containing material, and in which such exposure forms titanium silicide from the silicon-containing surface while not depositing titanium onto the electrically insulative surface. The embodiments may include atomic layer deposition processes, and may include a hydrogen pre-treatment of the silicon-containing surfaces to activate the surfaces for reaction with the titanium-containing material. Some embodiments include methods of titanium deposition in which a semiconductor material surface and an electrically insulative surface are both exposed to titanium-containing material, and in which a titanium-containing film is uniformly deposited across both surfaces.
摘要翻译：一些实施例包括钛沉积的方法，其中含硅表面和电绝缘表面都暴露于含钛材料，并且其中这种暴露从含硅表面形成硅化钛，而不将钛沉积在电绝缘表面。这些实施方案可以包括原子层沉积工艺，并且可以包括含氢表面的氢预处理以活化表面以与含钛材料反应。一些实施例包括钛沉积的方法，其中半导体材料表面和电绝缘表面都暴露于含钛材料，并且其中含钛膜均匀地沉积在两个表面上。

37. 发明授权

US07605417B2 Assemblies comprising magnetic elements and magnetic barrier or shielding at least partially around the magnetic elements 有权
标题翻译：包括磁性元件和至少部分地围绕磁性元件的磁屏障或屏蔽的组件
公开(公告)号：US07605417B2
公开(公告)日：2009-10-20
申请号：US11755677
申请日：2007-05-30
申请人： Joel A. Drewes
发明人： Joel A. Drewes
IPC分类号： H01L29/82
CPC分类号： H01L27/222 , G11C11/161 , H01L43/08 , H01L43/12
摘要： The invention includes a method of forming a semiconductor construction, such as an MRAM construction. A block is formed over a semiconductor substrate. First and second layers are formed over the block, and over a region of the substrate proximate the block. The first and second layers are removed from over the block while leaving portions of the first and second layers over the region proximate the block. At least some of the first layer is removed from under the second layer to form a channel over the region proximate the block. A material, such as a soft magnetic material, is provided within the channel. The invention also includes semiconductor constructions.
摘要翻译：本发明包括形成诸如MRAM结构的半导体结构的方法。在半导体衬底上形成块。第一层和第二层形成在块上方，并且在靠近块的衬底的区域上方形成。将第一层和第二层从块上方移除，同时将第一层和第二层的部分留在靠近块的区域上。从第二层下面移除第一层中的至少一些，以在靠近块的区域上形成通道。在通道内提供诸如软磁材料的材料。本发明还包括半导体结构。

38. 发明申请

US20080233700A1 Methods of forming integrated circuitry 审中-公开
标题翻译：形成集成电路的方法
公开(公告)号：US20080233700A1
公开(公告)日：2008-09-25
申请号：US11724784
申请日：2007-03-15
申请人： Eric R. Blomiley , Joel A. Drewes , D.V. Nirmal Ramaswamy
发明人： Eric R. Blomiley , Joel A. Drewes , D.V. Nirmal Ramaswamy
IPC分类号： H01L21/336
CPC分类号： H01L21/823425 , H01L21/823481 , H01L27/10873 , H01L27/1203
摘要： The invention includes semiconductor processing methods in which openings are formed to extend into a semiconductor substrate, and the substrate is then annealed around the openings to form cavities. The substrate is etched to expose the cavities, and the cavities are substantially filled with insulative material. The semiconductor substrate having the filled cavities therein can be utilized as a semiconductor-on-insulator-type structure, and transistor devices can be formed to be supported by the semiconductor material and to be over the cavities. In some aspects, the transistor devices have channel regions over the filled cavities, and in other aspects the transistor devices have source/drain regions over the filled cavities. The transistor devices can be incorporated into dynamic random access memory, and can be utilized in electronic systems.
摘要翻译：本发明包括半导体处理方法，其中形成开口以延伸到半导体衬底中，然后将衬底围绕开口退火以形成空腔。蚀刻衬底以暴露空腔，并且空腔基本上用绝缘材料填充。其中具有填充空穴的半导体衬底可以用作绝缘体上半导体型结构，并且晶体管器件可以形成为被半导体材料支撑并且在空腔之上。在一些方面，晶体管器件在填充腔体上具有沟道区域，在其它方面，晶体管器件在填充腔体上具有源极/漏极区域。晶体管器件可以并入到动态随机存取存储器中，并且可以在电子系统中使用。

39. 发明授权

US07402879B2 Layered magnetic structures having improved surface planarity for bit material deposition 有权
标题翻译：具有改进的钻头材料沉积的表面平面度的分层磁结构
公开(公告)号：US07402879B2
公开(公告)日：2008-07-22
申请号：US11134321
申请日：2005-05-23
申请人： Donald L. Yates , Joel A. Drewes
发明人： Donald L. Yates , Joel A. Drewes
IPC分类号： H01L29/82
CPC分类号： H01L27/222 , G11C11/15 , H01L21/7684
摘要： The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the flattened upper surface of the insulating layer and the first conductor and flattening an upper portion of the material layer while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.
摘要翻译：本发明提供了一种制造存储单元的一部分的方法，该方法包括提供一沟槽中的第一导体，其设置在绝缘层中并使绝缘层和第一导体的上表面平坦化，形成材料层在绝缘层和第一导体的平坦的上表面上方，并且使材料层的上部平坦化，同时在绝缘层和第一导体上完整地保留材料层的下部。

40. 发明授权

US07375388B2 Device having improved surface planarity prior to MRAM bit material deposition 有权
标题翻译：在MRAM钻头材料沉积之前具有改进的表面平面度的装置
公开(公告)号：US07375388B2
公开(公告)日：2008-05-20
申请号：US10734201
申请日：2003-12-15
申请人： Donald L. Yates , Joel A. Drewes
发明人： Donald L. Yates , Joel A. Drewes
IPC分类号： H01L29/76
CPC分类号： H01L27/222 , G11C11/15 , H01L21/7684
摘要： The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the flattened upper surface of the insulating layer and the first conductor and flattening an upper portion of the material layer while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.
摘要翻译：本发明提供了一种制造存储单元的一部分的方法，该方法包括提供一沟槽中的第一导体，其设置在绝缘层中并使绝缘层和第一导体的上表面平坦化，形成材料层在绝缘层和第一导体的平坦的上表面上方，并且使材料层的上部平坦化，同时在绝缘层和第一导体上完整地保留材料层的下部。

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